Abstract: A method and apparatus for testing complex processor-based computer modules and their associated computer systems by allowing the normal initialization path between a memory component storing code utilized during initialization and the processor to be interrupted and test code from an external test system to be substituted for initialization code. Following initialization, a two-way communication link between the processor and the test system is created to allow interactive testing and status reporting. The testing method and apparatus maximizes the likelihood of precisely identifying defects on the module under test.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. The termination further includes a circuit to linearize the impedance as a function of the reference voltage.

Abstract: A method of forming micro-trench isolation regions with a separation of 0.20 .mu.m to 0.35 .mu.m in the fabrication of semiconductor devices involves forming an silicon dioxide layer on select locations of a semiconductor substrate and depositing a polysilicon layer onto the silicon dioxide layer. A layer of photoresist is then deposited over select areas of the polysilicon layer and patterned to form micro-trench isolation regions of widths between about 0.2 .mu.m to about 0.5 .mu.m and aspect ratio of between about 2:1 to about 7:1. Thereafter, the isolation regions are etched for a time and pressure sufficient to form micro-trenches in the substrate surface. The micro-trenches will generally have a width ranging from about 1000 .ANG. to about 3500 .ANG. and depth ranging from about 500 .ANG. to about 5000 .ANG.. The layer of photoresist is then removed to expose the polysilicon layer and a channel stop implant is deposited and aligned with the micro-trenches.

Abstract: A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.

Abstract: A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled.

Abstract: A secure arrangement in which stations in a communications network are informed of the addresses of their neighbors by means of identifying messages transmitted by the stations. To prevent the insertion of illegitimate stations into the network, the system makes use of passwords included in the station-identifying messages. In networks where eavesdropping is possible, the passwords are encrypted versions of the identities of the stations transmitting the messages and in systems where stations can also be impersonated, the encrypted passwords also include time stamps.

Abstract: A monitor for packets on a local area network includes a set of logic circuits implemented in a computer chip, a memory interacting with the computer chip to provide monitoring data to the logic circuits, logic for receiving a packet from the local area network, and a parser to process bits of the packet as they are received, wherein the parser uses the monitoring data in conjunction with the received bits to provide forwarding data which indicates the type of packet received. The monitor uses the forwarding data to determine whether the received packet is stored in memory, discarded, or forwarded to other host computers in the network. The monitor uses type information from the forwarding data to maintain count information of the different types of packets which may be forwarded to a host computer or a remote monitoring device.

Abstract: A bridge-type primary switching circuit (12) is represented by a pulsed voltage source (VSW). The primary switched waveform is transformed to secondary circuit (14) using a transformer (T1) with the required turns ratio N and a center-tapped secondary winding (16). Half-bridge rectifier (18) formed by diodes (DR1) and (DR2) rectifies the secondary waveform and feeds the waveform through a low-pass filter (LF) and (CF) to obtain the desired DC output voltage. The snubber circuit (20) is represented by switch-diode-capacitor combinations (SA-DS1-CS1) and (SB-DS2-CS2) across each rectifier (DR1) and (DR2). Capacitances (CS1) and (CS2) are selected large enough such that their voltages remain essentially constant during a switching cycle. The controlled switches (SA) and (SB) are turned ON with a specific delay after the primary voltage reaches a magnitude close to the input voltage in order to allow the rectifier diodes (DR1) and (DR2) to be commutated.

Abstract: In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: A system and method of satisfying read and write requests is used in a system having a plurality of cache-equipped processors coupled into a hypercube structure via buses, where each processor is simultaneously coupled to other processors on other buses via gateway means. Read and write requests for a line of data from any of the processors are satisfied by forwarding an update or invalidate request for a given data block containing the line of data requested. This request is forwarded to all other buses on which the block is present. The present invention provides for responding to a read request for a line of data from a processor by forwarding the request, and resultant data, to one of the buses on which the block is stored, where each gateway responds to the request to forward the request along exactly one branch.

Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits--gate arrays--it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data.

Abstract: A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of the presence of any "1" in the n-2 low-order bits of the 2n-bit result. The presence of such a "1", indicates the so-called "sticky bit" is set. The sticky bit is calculated in a path separate from the multiply operation, so the n-2 least significant sums need not be calculated. This saves time and circuitry in an array multiplier, for example. In an example method, the difference between n and the number of trailing zeros, "x", in one of the n-bit operands is detected, by transposing the operand and detecting the leading one. The other operand is right-shifted by a number of bit positions equal to this difference. A sticky bit is generated if any logic "1's" are in the low-order n-x-2 bits fight shifted out of the second operand.

Abstract: A system for controlling the printing of a message having a plurality of strings of text and a plurality of parameters includes means for designating the locations of the strings of text, and the locations and formats of the parameters within the message. The system also includes means for switching the locations and the formats of the parameters after they have been designated, which may include a permutation specifier.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: A modular system for supporting equipment on a wall has support panels. Each panel includes a sheet having columns of keyholes, and a rear support surface lying in a plane parallel to and spaced behind the sheet. The rear support surface has keyholes near the top of the panel and fastener elements near the bottom of the panel. The fastener elements have the same spacing as the keyholes near the top of the panel. The fastener elements project from the plane of the rear support surface toward the front support surface to permit mating with keyholes near the top of another panel to be hung below it.

Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

Abstract: A line driver is coupled by a pair of signal lines to a receiver. Preprocessing circuitry, for processing signals arriving on the pair of signal lines at the receiver, includes regulating circuitry for regulating the voltage between the signal lines between predetetermined limits and thereby modifying the sensitivity of the system to compensate for changes in line conditions and reject interference when the line driver is powered down. The regulating means includes: bias circuitry, for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away from the triggering voltage level so that it is not triggered by noise; and bias limiting circuitry, responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level. A resistor is connected between the two signal lines.

Abstract: A transient voltage suppression circuit consists of energy dissipation components with one end connected either to a line or a neutral wire of a power line and the other end connected to a reed switch which, in turn, is connected to ground. The reed switch, which is an encapsulated switch consisting of two metal strips with a gap between them, is in an open position, and accordingly, does not under normal operating conditions provide a path to ground for the associated energy dissipation components. The energy dissipation components thus do not conduct. When a transient having a sufficiently high voltage occurs between the line or neutral wires and the ground wire, it causes the reed switch to conduct momentarily, that is, spark, across the gap. The switch momentarily forms a path to ground and allows the associated energy dissipation components to shunt a transient current away from protected appliances.

Abstract: A card cage formed of mating, identical halves provides parallel slots for circuit boards carrying snap-on retainer clips with integral pawl-like clasps which lock over ridges on the exterior of the card cage. The clip is released from the cage by squeezing the clasps with one hand before withdrawing the circuit board. Slotted side brackets capture mating ribs on the card cage halves to assemble and mount the card cge to a wiring clost panel.