Abstract: A multi-sensor system for the real-time embedded monitoring of an object senses mixed-mode object conditions. Various sensors separately provide disparate analog signals representing different measurable attributes regarding the sensed object. For example, such sensors may separately sense temperature, pressure, or other biometric value. Then, according to a specified rule set or other qualifying parameters, a digital signal is generated by a processor or controller to indicate one or more condition of the sensed object according to certain sensor input values. Additionally, such multi-sensor scheme may be coupled to a digital network or otherwise coupled thereto for simulation and/or communication applications.

Abstract: The invention discloses a relative structure placement of datapath of cell instances in a column structure, a row structure, or an array structure. To encourage placement of a desirable structure, pseudo cells, pseudo pins, and pseudo nets are selected to be placed at certain locations with respect to real cell instances. The end result produces a cluster of real cell instances that form a desirable structure while minimizing the length of nets. The invention further discloses a non-uniform partitioning of a density map for calculating a force update vector. The partitioning is taken over a region A to compute Riemann sum approximations of a function F over the region A. A force update vector is calculated for a given cell instance within the region A where neighboring cell instances have an exponentially larger grid size as cell instances extend further away from the given cell instance.

Abstract: A method and apparatus for resolving priority among a plurality of data values. The priority resolution method of the invention analyzes the data values one bit at a time, starting from the most significant bit. In one embodiment, at an initial analysis step, the method determines whether the most significant bits of the data values are asserted. If at least one of the most significant bits is asserted, the data values that have unasserted most significant bits are eliminated from consideration. If none of the most significant bits is asserted, none of the data values will be eliminated at the initial step. The same analysis steps are repeated for each successive bit until only the largest data values remain. The priority resolution method of the present invention may be used to determine the smallest data value. In that embodiment, the data values are first bit-wise inverted.

Abstract: A fingerprint recognition method includes iterative gamma correction that compensates moisture effect, feature extraction operations, directional morphological filtering that effectively links broken ridges and breaks smeared ridges, adaptive image alignment by local minutia matching, global matching by relaxed rigid transform, and statistical matching with Gaussian weighting functions.

Abstract: A digital, radio-frequency (RF) transceiver is modified by coupling an infra-red (IR) communication subsystem thereto. The subsystem includes an IR transmitter and receiver which may be coupled selectably by a switch to a data signal channel or source in the transceiver. Preferably, the IR receiver includes an inductor and a diode coupled in parallel, such that the IR receiver detects an IR signal, in significant part, by resonating such signal substantially at a detection or RF baseband frequency.

Abstract: In a sequential-access memory device having storage registers located at consecutively addressable rows, data are accessed from odd and even banks by enabling consecutive rows during a common read cycle. In particular, by coupling data lines separately to odd and even register rows in the memory device, data may be accessed selectably from consecutive register rows with reduced access time.

Abstract: An amplifier circuit providing high power efficiency and an improved phase margin includes a transconductance input stage, one output of which is connected to an input of a class AB amplifier gain stage to form a compensation node, and the other output of which drives a current gain means, with the outputs of the current gain means and the class AB amplifier forming a current summing output node that is coupled to the compensation node through a compensation capacitor. The phase margin of the amplifier circuit is optimized by selecting the gain of the current gain means to be approximately equal to one plus the ratio of the capacitance of the load to the capacitance of the compensation capacitor.

Abstract: A method for duplicating data on a rotating magnetic disk in sectors on concentric tracks so that the sectors are aligned with each other from track to track and referenced to an index mark. The index mark is sensed as the disk rotates. The time elapsed between sensed index marks is counted to define the angular displacement of the disk. A magnetic head is moved successively to the tracks on the disk. Data to be duplicated is recorded in sequence, sector by sector, on the respective tracks beginning at different offsets from the index mark such that recording begins with the next sector encountered after the head arrives at the respective tracks.

Abstract: A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.

Abstract: A system and a method are described for optimizing the sequencing and time requirements for compiling large sets of source code residing in multiple hierarchical file directories using an abstracted logical description of the hierarchical file relations existing between directories. The system consists of a logic processor working in concert with input and output file registers, a match register, and an abstracted tree register for the purpose of creating a identifying, comparing, and sequencing file names in a final description of the global directory. The method iteratively identifies the primary input files and the intermediate input files for a given output file for each of a series of directories, inverts the casual relationship between the output file and its intermediary input files, and accumulates and stores these relationships in a sequential manner for subsequent use.

Abstract: Internal and external magnetic screens made of magnetic permeable material are added between the discharge chamber and the internal and external sources of magnetic field, respectively. A longitudinal gap is maintained between the screens and their respective internal and external poles, that does not exceed half the distance between the internal and external poles. The exit end part of the internal magnetic screen is placed closer to the middle point of the accelerating channel than the internal pole. The walls of the exit end part of the discharge chamber are constructed with an increased thickness, and extend beyond the planes that the poles lay. The magnetic screens can be located with a gap relative to the magnetic path if connected by a bridge between the screens. The discharge chamber, the anode, and the magnetic system are symmetrically designed relative to two mutually perpendicular longitudinal planes.

Abstract: A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

Abstract: An apparatus and method for improved efficiency of operation of a circuit simulator. The simulation engine processor sends signals via flag registers to the component model processors to indicate which type of response is required from each component model. The component model processors send back only the requested response, thus minimizing processing time by avoiding generating response types that are not needed. Flexibility is enhanced by centralizing tasks in the simulation engine rather than in the component models, in order to facilitate experimentation and variation in circuit configurations without extensive modifications of component model design.

Abstract: An improved apparatus and method for mounting an electrical box between studs in a wall is disclosed. The apparatus of the invention is a mounting bracket comprising a relatively flat, elongated frame having a front planar face, a rear planar face, and a first and second opposing ends attachable to two corresponding wall studs. The frame also has a central cut-out portion which defines a top edge and a bottom edge. An electrical box and its accompanying faceplate may be mounted between two wall studs by first attaching the bracket of the present invention to the wall studs. The open front end of the box is then placed flush against the rear face of the bracket such that a top portion of the box contacts the top edge of the bracket and a bottom portion of the box contacts the bottom edge of the bracket.

Abstract: A method and apparatus for providing a lower frequency signal with reference to a higher frequency signal are disclosed. The apparatus of the invention comprises an oscillating signal generator, an integer logical divider, and a signal combiner. The signal generator receives an input voltage and, in response thereto, generates a first output oscillating signal and a second output oscillating signal, both having a first frequency. The two oscillating signals are separated by a ninety-degree phase shift. The integer logical divider receives the two oscillating signals and provides two output divided signals in response. The first divided signal is representative of the first oscillating signal except that its frequency is one-third the frequency of the first oscillating signal. Likewise, the second divided signal is representative of the second oscillating signal except that its frequency is one-third that of the second oscillating signal.

Abstract: An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes.

Abstract: A method and apparatus for determining the quality of a colloidal suspension. According to the method of the present invention, an oscillating input electrical signal is applied simultaneously to a sample of the colloidal suspension to be tested and to a reference solution. The reference solution is substantially identical to the colloidal suspension except that the colloidal particles have been removed. The input signal causes charge particles and molecules within both substances to move, thereby, giving rise to electrical currents. Thus, a test current is extracted from the colloidal suspension and a reference current is extracted from the reference solution. Thereafter, a differential output current is derived by substracting the reference current from the test current. The peak-to-peak magnitude of the differential output current is measured, and the phase of the output current is compared to the phase of the input signal to determine the difference in phase between the two signals.

Abstract: A data communications system is overlaid on a voice-based trunked radio system. Digital data packets are transmitted over available radio channels, thereby enabling data communication between a host dispatch system and mobiles and a base station in the trunked radio system. Radio channels associated with trunked channel groups are accessed when available by a communications controller. The communications controller is configured to communicate with various mobile units of the trunked radio system over available radio channels through multiple radio communication links. Radio channels are monitored to detect when the radio channels are presently unused for voice transmission and thereby accessible for data overlay. In particular, when the data overlay system detects that the transmission of analog voice information ceases over a particular radio channel, the trunked channel group association of that particular radio channel is caused to be switched from a voice group to a data group.

Abstract: Apparatus 70 interfaces between port 20 of personal computer 10 and peripheral device 40 connectable to port 20. Transmit and receive data signals (TXD, RXD) are transmitted and received between port 20 and device 40 to pass through without substantial modification by apparatus 70. Protocol signals are transmitted by port 20 and processed to provide digital data signals. The protocol signals include a Request To Send (RTS) signal and a Data Terminal Ready (DTR) signal, whereby the apparatus processes RTS signal to provide a protocol clock signal and processes DTR signal to provide a protocol data signal. The protocol signals are monitored to identify a protocol signal pattern. Upon identifying such pattern within a particular protocol signal, a particular digital data signal is extracted from the protocol signal. The extracted digital data signal may then be converted to analog signals which are applicable to produce sound from speaker 80.

Abstract: Apparatus and methods for reducing the quantization error in shift-matrix finite impulse response (FIR) filters (210) operate on a sampled analog signal (11) converted to a sequence of digital signal samples (13). A weight conversion device (23) converts a weight signal W comprising a sequence of tap weights W.sub.i into both a corresponding series of logarithmically-encoded weights W'.sub.i and a series of weight error values .DELTA.W.sub.i. A multiplication device (30) multiplies each of the digital signal samples (13) with the first series of logarithmically-encoded weights W'.sub.i and provides the results to an accumulator (26). A signal encoding device (40) converts the digital signal samples (13) into a sequence of logarithmically-encoded digital signal samples (42). A quantization error correction device (220) multiplies each of the weight error values .DELTA.W.sub.i by the logarithmically-encoded digital signal samples (42) and also provides the results simultaneously to the accumulator (26).