Abstract: A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

Abstract: A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array.

Abstract: A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

Abstract: A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry.

Abstract: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result.

Abstract: A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

Abstract: A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memory operand into the microprocessor from memory at the source address and to calculate a destination address. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to memory at the destination address calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively calculates the source address and loads the memory operand into the microprocessor from memory at the source address. A second execution unit also receives the first microinstruction and calculates the destination address.

Abstract: A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed differences: determining whether the borrow bit indicates the packed difference is positive or negative and selecting a value in response to the determining, the value comprising the packed difference if the associated borrow bit is positive and a complement of the packed difference if the associated borrow bit is negative; adding the selected values to generate a first sum and a first carry and in parallel adding the borrow bits to generate a second sum and a second carry; adding the first and second sums and the first and second carries to generate a result of the instruction; storing the result in a register of the microprocessor.

Abstract: A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.

Abstract: A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.

Abstract: A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state.

Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Abstract: A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register.

Abstract: An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.

Abstract: A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction translator translates instructions of the ISA. The ISA includes a distinct instruction that instructs the microprocessor to write the bytes from the buffer to a first user-visible register of the microprocessor and to load the count from the counter to a second user-visible register of the microprocessor. The count is unspecified by the instruction and may be between zero or more. In another embodiment, the instruction instructs the microprocessor to store a number of random data bytes specified from the buffer to a destination specified by the instruction, wherein the specified number may be greater than the maximum amount of bytes the buffer can hold.

Abstract: A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture.

Abstract: A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also includes an instruction translator that translates an instruction specifying an address in a memory coupled to the microprocessor. The microprocessor also includes a store unit that stores to the memory at the address the variable number of bytes of random data from the storage element in response to the instruction translator translating the instruction. In one embodiment, the microprocessor atomically stores the count and the bytes accumulated in said buffer to the system memory. In one embodiment, an interrupt unit disables interrupts after the instruction translator translates the instruction and enables interrupts after execution of the instruction.