Abstract: A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and controls clock generation circuitry of the microprocessor to output a lower one of its M core clock signal frequencies as necessitated by a transition to the next lower output voltage level until the temperature drops below the first temperature. The control circuit detects that the temperature has dropped below a second temperature and responsively iteratively controls the voltage source to output a next higher output voltage level and controls the clock generation circuitry to output a higher core clock signal frequency as permitted by the next higher output voltage level until the operating temperature rises above the second temperature. The M frequencies comprise a highest, lowest, and plurality of intermediate frequencies.

Abstract: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.

Abstract: A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency being the maximum frequency at which the microprocessor will reliably operate at the first temperature and the first voltage. Operating point data also includes a second temperature at which the microprocessor will reliably operate at a second frequency and a second voltage, the second frequency being greater than the first frequency and the second temperature less than the first temperature. A control circuit causes the microprocessor to operate at the second voltage and frequency rather than the first voltage and frequency in response to detecting that while operating at the first voltage and the first frequency the operating temperature dropped below the second temperature.

Abstract: A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N?1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.

Abstract: A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.

Abstract: A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.

Abstract: A microprocessor capable of dynamically reducing its power consumption based on its varying operating temperature includes a temperature sensor that monitors the microprocessor's operating temperature and a control circuit that includes operating point data. The operating point data includes a first voltage at which the microprocessor may reliably operate at a frequency and at a first temperature, and a second voltage at which the microprocessor may reliably operate at the frequency and at a second temperature. The second temperature is less than the first temperature and the second voltage is less than the first voltage. The control circuit causes the microprocessor to operate at the frequency and at the second voltage rather than at the first voltage when the operating temperature drops below the second temperature while operating at the frequency and at the first voltage.

Abstract: A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.

Abstract: A microprocessor for predicting return instruction target addresses is disclosed. A branch target address cache stores a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and provides a prediction of the target address of the return instruction from the target address predictions and provides a corresponding override indicator from the override indicators. Each has a true value when the return stack has mispredicted the target address of the corresponding return instruction for a most recent execution of the return instruction. A return stack also provides a prediction of the target address of the return instruction. Branch control logic causes the microprocessor to branch to the prediction of the target address provided by the BTAC, and not to the prediction of the target address provided by the return stack, when the override indicator is a true value.

Abstract: A microprocessor capable of dynamically reducing its power consumption based on its varying operating temperature includes a temperature sensor that monitors the microprocessor's operating temperature and a control circuit that includes operating point data. The operating point data includes a first voltage at which the microprocessor may reliably operate at a frequency and at a first temperature, and a second voltage at which the microprocessor may reliably operate at the frequency and at a second temperature. The second temperature is less than the first temperature and the second voltage is less than the first voltage. The control circuit causes the microprocessor to operate at the frequency and at the second voltage rather than at the first voltage when the operating temperature drops below the second temperature while operating at the frequency and at the first voltage.

Abstract: A Fibre Channel (FC) controller shareable by a plurality of operating system domains (OSDs) within a load-store architecture is disclosed. The controller has a FC port that obtains a plurality of FC port identifiers for association with respective ones of the OSDs. A load-store bus interface is the target of a load-store transaction on a load-store bus from each OSD. The load-store transaction includes a command to perform an I/O operation with a remote FC device. Association logic populates an S_ID field of a FC frame with the FC port identifier associated with the respective OSD that initiated the command. The FC port transmits the FC frame on the FC port to the remote FC device. In one embodiment, the controller interfaces to an Advanced Switching fabric to receive packets encapsulating load-store transactions from the OSDs. Each packet includes an identifier identifying the OSD initiating the transaction.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor also includes a cache memory, comprising an array of storage elements for storing cache lines, indexed by an index input. One of the storage elements of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer is storing a replacement candidate line for the prefetched cache line. The microprocessor also includes control logic that determines whether the replacement candidate line in the cache memory is invalid, and if so, replaces the replacement candidate line in the one of the storage elements with the prefetched cache line from the prefetch buffer.

Abstract: A method for adopting an orphaned I/O port of a storage controller is disclosed. The storage controller has first and second redundant field-replaceable units (FRU) for processing I/O requests and a third FRU having at least one I/O port for receiving the I/O requests from host computers coupled to it. Initially the first FRU processes the I/O requests received by the I/O port and the third FRU routes to the first FRU interrupt requests generated by the I/O port in response to receiving the I/O requests. Subsequently, the second FRU determines that the first FRU has failed and is no longer processing I/O requests received by the I/O port, and configures the third FRU to route the interrupt requests from the I/O port to the second FRU rather than the first FRU, in response to the determining that the first FRU has failed.

Abstract: A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes program instructions from a CPU memory coupled to it. The CPU programs the bus bridge with window information defining a window of locations within the CPU memory, which is less than an entirety of the CPU memory. The bus bridge receives data on the link from the other controller and if the header of a packet containing the data indicates it is destined for the CPU memory, the bus bridge translates the address of the data so as to write the data safely to the CPU memory, but only within the window and nowhere else within the CPU memory.

Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.

Abstract: A SAS expander includes SAS PHYs for transceiving signals with SAS devices on corresponding SAS links coupled to the SAS PHYs. The SAS expander includes status registers that provide fault detection parameters concerning communications on the SAS links. A microprocessor of the SAS expander identifies faulty communications on one of the SAS links, based on the fault detection parameters, and disables a corresponding one of the SAS PHYs coupled to the SAS link on which the microprocessor identified the faulty communications. The microprocessor may also report the PHY disabling to a SAS initiator. The microprocessor may also re-enable the PHY after corrective action is taken, such as in response to user input, an indication from a SAS device, or automatically detecting the corrective action. The expander may also automatically take the corrective action. The fault detection parameters may include error counters and corresponding thresholds, interrupt indicators, and state values.

Abstract: A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

Abstract: An active-active RAID system includes first and second active-active RAID controllers which efficiently share access to SATA drives. SAS expanders connect the RAID controllers to the drives. The controllers establish an affiliation within the SAS expanders with respectively-owned first and second subsets of the SATA drives. The controllers directly transmit to the SAS expanders commands destined for affiliated drives, but forward to the other RAID controller, via an inter-controller communications link, commands destined for unaffiliated drives for transmission by the other RAID controller. The controllers handle drive ownership changes by clearing previously-established affiliations, updating ownership data stored on the drives, including forwarding the update commands as necessary, and re-establishing affiliations based on the new ownership.

Abstract: A fault tolerant storage controller having a processor, redundant copies of a stored program, and a timer that automatically runs when the processor is reset is disclosed. Selection logic selects a first copy of the program to boot on the processor. If the timer expires before the first copy successfully boots, the timer resets the processor and re-enables itself to run again. This time, selection logic selects a second copy of the stored program. In one embodiment, the program comprises separate loader and application programs, each having a redundant copy. The loader re-enables the timer when jumping to the first copy of the application code. If the timer expires before the first application copy successfully boots, the timer resets the processor and re-enables itself to run again. This time, the loader selects a second copy of the application program. In one embodiment, the redundant copies are stored in separate FLASH devices; in another, in distinct regions of the same FLASH device.

Abstract: A Fiber Channel (FC) controller shareable by a plurality of operating system domains (OSDs) within a load-store architecture is disclosed. The controller includes a plurality of control/status register (CSR) banks. A respective one of the CSR banks is used by each OSD to request the controller to perform I/O operations with remote FC devices. A load-store bus interface receives from a load-store bus load and store transactions from each OSD. Each transaction includes an OSD identifier identifying the OSD that initiated the transaction. The bus interface directs the transactions to the respective CSR bank based on the OSD identifier. A FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, the controller includes a shared I/O switch coupling the OSDs thereto.