Abstract: A bridge-type main valve located at a connecting outlet between a vacuum chamber and a main vacuum pump, and having a rod of an electric cylinder driven by a stepper motor connected to a valve seat for opening and dosing the connecting outlet so that the driving direction and a closing surface of the valve seat form a right angle. A piston may be attached to the rod, and a cylindrical housing fitted in the piston so that the piston and the cylindrical housing form a pressurized air pumping chamber for moving the rod and the valve seat in the outlet closing direction. The valve can achieve fine pressure adjustment without any variable orifice by stopping a valve seat at an arbitrary (not stepwise) position.

Abstract: A digital signal processor evaluation chip has a sequencer for fetching and decoding instructions, and a processor core for executing the instructions. When the sequencer attempts to fetch an instruction from a preset break address, a register transfer instruction is supplied in place of the program instruction at that address, then clock input to the sequencer is halted. After the processor core has executed the register transfer instruction, clock input to the processor means is also halted, leaving the data transferred by the register transfer instruction available to be read.

Abstract: Process for the purification of inert gases containing impurities of organic nature particularly of gas (nitrogen) coming from solid state polycondensation reactors or polyester resins including the gas treatment with the stoichiometric quantity (or slightly higher) of oxygen as regards the present impurities at a temperature between 250.degree. and 600.degree. C. by using Pt or Pt/Pd catalysts supported on a porous solid and the gas recycling directly to the polycondensation reactor before drying to eliminate the water produced during the reaction of impurities oxidation.

Abstract: A cache memory device stores image data which are arranged corresponding to address data having first and second two-dimensional coordinate data. The image data are divided into a plurality of first groups in accordance with the first two-dimensional coordinate data, with the first groups further divided into a plurality of second groups in accordance with the second two-dimensional coordinate data. The cache memory device includes an image data memory for storing a given image data therein, which is divided into a plurality of block areas arranged in two dimensions. The reading and writing of image data from and to the image data memory is controlled by a central processing unit. A cache storage, comprising a cache memory, an address data decoding circuit, an address matching circuit and a control circuit, is coupled between the image data memory and the central processing unit by way of buses.

Abstract: A sports installation is in the form of a rectangular-box-shaped court with at least one transparent wall and a goal structure at each end, the goals occupying the entire length of the end walls and projecting from the rectangular-box-shape.

Abstract: A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

Abstract: A process and device for shaping the end of a tube with an oblong cross-section to a circular cross-section, where the shaping occurs in a single radial compression stage from the exterior. The tube is disposed with its shortest axis in correspondence with two fixed opposite surfaces, having a circular profile with a radius of curvature which is approximately equal to the radius of the circular section of the tube which is to be obtained. A radial compression is then exerted along the longest axis of the oblong section of the non-deformed tube by a pair of shaping surfaces having an angular extension which is complementary to those of the fixed opposite surfaces.

Abstract: A semiconductor device having a ferroelectric film or a polycrystalline silicon gate, a humidity-resistant hydrogen barrier film, like TiN film, TiON film, etc., formed by hydrogen non-emission film forming method over the ferroelectric film or the polycrystalline silicon gate.

Abstract: A Schmitt trigger circuit has a field effect transistor coupled between a first fixed potential and an output terminal, and a variable negative resistance circuit coupled between the output terminal and a second fixed potential; the gate of the field effect transistor and the control input of the negative resistance circuit are coupled to the input terminal of the Schmitt trigger circuit; wherein the negative resistance circuit includes a first field effect transistor coupled between the output terminal and the second fixed potential, and a gate coupled to an internal node; a second field effect transistor coupled between the internal node and the second fixed potential, and a gate coupled to the input terminal; and a third field effect transistor coupled between the first fixed potential and the internal node, and a gate coupled to the output terminal.

Abstract: Starting from a sequence of values of indicated torque detected for each expected combustion in the engine a cycle signal is generated as a combination of at least two successive values of the said sequence. The peak value of the said cycle signal is then compared with a comparison threshold chosen preferably in proportion of the fuel injection duration into the cylinders. Misfires are identified preferably from the result of a comparison between the said peak value and the said comparison threshold which differs from the result of comparison in the presence of regular operation of the engine.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A load circuit which can tolerates large current and voltage swings before saturation begins includes a field effect transistor having a source coupled to a power supply, a drain coupled to an input terminal which receives signals from a memory circuit data line, and a gate coupled to the drain through a level shifter.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: The voltage reference generator of the present invention includes a plurality of p-channel transistors configured to act as resistors. Switching transistors, responsive to input signals, are utilized to bypass the resistors when in the "on" state, and enable the resistor when in the "off" state. Thus, when enabled, the resistors become part of a total resistance value in a branch of a voltage divider circuit. A minimum amount of space is used on an integrated circuit because the switching transistors are of the same type as the transistors which are configured to act as resistors.

Abstract: A speech recognition system starts by training hidden Markov models for all triphones, diphones, and phonemes occurring in a small training vocabulary. Hidden Markov models of a target vocabulary are created by concatenating the triphone, diphone, and phoneme models, using triphone models if available, diphone HMMs when triphone models are not available, and phoneme models when neither triphone nor diphone models are available. Utterances from the target vocabulary are recognized by choosing a model with maximum probability of reproducing quantized utterance features.

Abstract: A level shifter includes an N-channel enhancement-mode field effect transistor (40), a P-channel depletion-mode field effect transistor (38), and a current mirror (42) coupled to the source of the enhancement-mode transistor and the drain of the depletion-mode transistor; wherein the gates of the transistors are coupled to an input terminal and the source of the enhancement-mode FET is coupled to an output terminal to provide a level shifted output signal.

Abstract: A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

Abstract: An article of sport footwear in particular a ski boot, with a boot shell in which a boot entrance is defined for receiving the skier's leg, and with a plate-like lug associated with the shell at the location of the entrance to provide predetermined conditions of support for the skier's leg, wherein the lug is pivotable relative to the shell into at least two working positions where it presents different portions to the entrance, thereby varying the support conditions provided for the skier's leg accordingly.

Abstract: An inverting amplifier includes a negative resistance circuit coupled between an output node and a power supply to provide a variable negative resistance in response to an input potential, and a resistance element connected between the output node and ground.

Abstract: Column circuitry for a CMOS static RAM includes a bit line clamp combined with a bit line current source regulated by a voltage reference which tracks changes in transistor characteristics. Separate data read and data write lines are provided, with a differential amplifier for each pair of bit lines. The data read lines are coupled to compensated current source loads, and the differential amplifiers are couplled to switching transistors which are also compensated for transistor characteristic changes, Each bit line pair has a sneak capacitance prevention transistor so that in non-selected columns the bit line pairs are coupled together allowing the memory cells therein to pull down all of the bit lines. This isolates the read lines from unwanted capacitance in the differential amplifiers of each of the non-selected columns, Further, a VCC protection circuit is provided.