Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: A semiconductor device comprised of a transistor (TR) having a gate electrode, a source region and a drain region, and a ferroelectric capacitor formed above a local oxide film. The capacitor has a ferroelectric film, and upper and lower electrodes that sandwich the film therebetween. The lower electrode and the source region are connected to each other through a wiring or interconnection which is formed of a conductive reaction-preventing film with an Al wiring electrode stacked thereon. The conductive reaction-preventing film is formed of TiN, MoSi, W, etc. If an annealing treatment is carried out for the purpose of improving the characteristics of the semiconductor device or a final protection film is formed after the formation of the wiring electrode, the wiring electrode and the upper electrode do not react with each other. Thus, excellent characteristics of the ferroelectric film are obtained so that a highly integrated ferroelectric memory having high performance can be formed.

Abstract: A pie chart processor obtains the coordinates of a point indicated by a pointing device, calculates the distance between this point and the center of a pie chart, and compares this distance with the radius of the pie chart to decide whether the point is located in the pie chart. If the point is in the pie chart, the processor tests slices of the pie chart to find a slice containing the point, then executes a program corresponding to that slice.

Abstract: In a method of reading data comprising the steps of selecting a given column line and a bit line adjoining to the column line among a plurality of column lines (102-1.about.102-3) and bit lines (101-1, 101-2)based on column selection signals (Y.sub.1 .about.Y.sub.3), selecting a given row line among a plurality of row lines (103-1.about.103-n) based on row selection signals (X.sub.0 .about.X.sub.n) and reading out data which is stored in memory cells (104-01.about.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: A method for reading data for a semiconductor memory device including steps of selecting a plurality of memory locations on which data are stored by word-lines and bit-lines, and reading the data from the bit-lines is provided, which comprises the steps of precharging the word-line by activating the first precharge signal; precharging the bit-line by activating a second precharge signal after a lapse of predetermined time since the first precharge signal has been activated; selecting a predetermined memory location in response to address signals; and reading data stored on the memory location from the bit-line by inactivating the first and second precharge signals.

Abstract: A process for sealing the rotor of a turbine which uses wet geothermal steam under pressure in which the said rotor is provided with a plurality of adjacent labyrinth sealing rings interposed with passages which extend radially of the rotor itself. The process provides at least one step in which a flow of steam is introduced into one of the said radial passages and made to pass through the labyrinth of at least one of the said sealing rings, being throttled with a drop in pressure and reduction in temperature. The portion of steam which has been throttled is collected through another of the said radial passages and exhausted or recycled to the turbine at an intermediate stage having the same pressure as the steam. The pressure and temperature values reached by the steam after throttling are such as to maintain it in a wet state. In this way, as the steam always stays wet, the salts in the original geothermal steam remain dissolved and are not deposited, thus allowing the seals to operate correctly.

Abstract: A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal.

Abstract: In a semiconductor integrated circuit device, a sense amplifier (30A) is capable of operating selectively with a first operating point (VR1) or with a second operating point (VR2) at the time of address change. A control circuit (80) detects the output data output at the preceding read cycle and causes the sense amplifier to operate with said first operating point in accordance with the output data of the preceding read cycle. A match detecting circuit (210) may be provided to generate a match signal or a mismatch signal depending on whether or not the input and output of a data input delay circuit (200) match each other. When the mismatch signal is generated, a transfer gate (220) is turned off and a latch circuit is made operative so that the write data of the preceding cycle is held on a write data line connected to the output of the transfer gate.

Abstract: Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs from varying too far in a sense amplifier used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.

Abstract: A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the

Abstract: A tobacco bale slicing machine having a support structure with an inlet opening for the insertion of a bale, and with an outlet portal. A conveyor transfers a bale from the inlet opening to the outlet portal in which there is a guillotine-like cutting device. A thrust device bears against the rear end surface of the bale to urge it towards and through the outlet portal in a controlled manner. The thrust device includes a motor-driven carriage disposed above the conveyor and has a thrust member mounted on an arm which moves between a raised and lowered position. When in a lowered, working position the thrust member can be brought to bear against the rear end surface of a bale carried by the conveyor in order to urge it toward the outlet portal in a controlled manner.

Abstract: In a fuse programmable voltage generator providing an optimal internal voltage VCCINT, a counter outputs various values to a voltage down comparator to output corresponding internal voltages VCCINT until a desired voltage is obtained. Once the desired internal voltage VCCINT is determined, the counter is disabled and a fuse circuit is configured to substantially maintain the output of the desired internal voltage VCCINT.

Abstract: Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

Abstract: An output buffer circuit has a pull-up output transistor controlled by a first node and a pull-down output transistor controlled by a second node. The first node is coupled to the second node through a switching stage controlled by feedback from the output terminal. When the output buffer circuit is switched between the high and low output states, the switching stage is initially on, switches off shortly after the potential of the output terminal begins to change, then switches on again when the output terminal reaches a certain intermediate potential.

Abstract: A foamed cellular material from polyester resins is obtained by extrusion foaming of polyester resins having melt strength higher than 8 centinewton, intrinsic viscosity greater than 0.8 dl/g and complex melt viscosity higher than 25,000 poises.

Abstract: A sense amplifier control circuit supplies a first potential to the sense amplifiers of a semiconductor memory through a set of first control transistors, each coupled in parallel to at least two and at most four sense-amplifier nodes. The first transistors are switched by a first control signal line. A second potential may be supplied to the sense amplifiers through a similar set of second control transistors, which are switched by a second control signal line. The first and second control signal lines may be driven independently, or one or both control signal lines may be driven by a set of drivers coupled in parallel between the two control signal lines.

Abstract: A method of remote-registering a telephone number or similar communication control information at a mobile station such as an automobile telephone, and circuitry therefor. The mobile station is conditioned for a remote register mode in response to a command signal which is transmitted from a remote station. A modulated multifrequency signal corresponding to the modulated communication information is sent from the remote station to the mobile station which is in the remote register mode over a communication channel. The mobile station demodulates the modulated multifrequency signal to produce the original multifrequency signal, converts the demodulated multifrequency signal to a digital signal, and then stores the digital signal in a memory.

Abstract: The horn includes a support casing (1 to 3) in which the peripheries of two facing diaphragms (10, 11) are restrained, a chamber (12) of variable volume being defined between the diaphragms (10, 11) and communicating with a sound-emission duct (50, 51, 70). Respective, opposed ferromagnetic armatures (17, 18) are connected to the diaphragms (10, 11). When a control solenoid (15) is excited by an intermittent current, it causes the armatures (17, 18) to move in opposition and the diaphragms (10, 11), to vibrate in counterphase.