Abstract: A programmable device having a processing core is configured to use a subset of configuration memory cells as read/write memory. The subset of memory cells is a don't care set that includes configuration memory cells that can be set or reset without modifying the function or behavior of the configured circuits of the programmable device.

Abstract: A configurable voltage bias circuit is used to control gate delays in buffers by adjusting the supply voltage of the buffers. The programmable voltage bias circuit includes a configurable voltage divider, which receives an input supply voltage and generates an output supply voltage, and a configurable resistance circuit, which is coupled between the configurable voltage divider and ground. By using a temperature dependent reference voltage to generate the input supply voltage, the output supply voltage is also made to be dependent upon temperature. The programmable voltage bias circuit of the present invention uses the temperature dependence of the output supply voltage to make the gate delays of the buffer temperature-independent.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: Apparatus, methods and computer program products are disclosed that track movement or a moving object through a warped video image. The warped video image can result from a video camera attached to a warping lens such as a wide-angle lens or panoramic lens. Some embodiments allow a user to select the portion of the image that interests the user for tracking. Other embodiments automatically select and track movement through the warped video image without input from a user. Still other embodiments track when movement comes into proximity with an area-of-interest and will raise an alarm that can be used to start recording of the warped video image or to trigger other alarm responses. Yet other embodiments change the bandwidth allocated to portions of the warped video image sent over a network responsive to the tracked movement so that the movement stays in a quality view.

Abstract: A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.

Abstract: A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.

Abstract: A method and system is provided for calculating motion vectors of macroblocks in a digital image of a digital video stream. The method and system reduces the computational overhead of calculating motion vectors by limiting the search for the origin block to a coarse search window and a fine search window within the coarse search window. The difference measure is computed for only a subset of pixel blocks within the coarse search window to reduce the computational overhead. However, to increase accuracy, the difference measure of all the pixel blocks in the fine search window are computed. The pixel block having the smallest difference measure is selected as the origin block.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: A method and system enhances the color of an image by manipulating the chrominance and/or luminance signals of the image. Specifically, a color enhancement system sharpens color changes for better picture quality on digital display systems. In one embodiment of the present invention, color changes are detected by a color change detection unit. If the color changes are significant, a color change sharpening unit sharpens the color change to enhance the image.

Abstract: A method and system of noise filtering is provided. The pixels of a first filter mask are separated into groups based on luminance . . . The sizes of each group is determined and a largest group is selected. The distance of each group of pixels from the largest group is also calculated. Pixels in groups that are small compared to the largest group and far from the largest group are tagged as noisy. After tagging the noisy pixels, additional filtering can be applied to the pixels of first filter mask without degradation from the tagged pixels.

Abstract: A method and system for filtering a texture map representing three-dimensional objects or texture projections of environments is provided. Specifically, the three-dimensional object or texture projection is divided into a plurality of faces, which are stored in the texture map. Filtering of a texel or pixel near the edge of a first face includes a plurality of texels from the second face. A pointer and a stride parameter are stored in the texture map and used in the selection of the texels from the second face to be used in the filtering of the texel in the first face.

Abstract: An immersive video system is provided which enables a user to interact with immersive video on a variety of platforms. To accommodate different types of platform components, the resolution of the immersive video may be changed. In one embodiment, a pair of immersive videos, one of the immersive videos having a 360° field of view, are simultaneously played in a standard display software program. In another embodiment, a single immersive video mapping an environment greater than 360° is played in a standard display software program. The display software program can be chosen such that it is supported by a variety of platforms. A view window associated with the standard display software program defines the portion of the immersive video shown to the viewer. A control adjusted by the viewer pans the view window around one of the pair of immersive videos.

Abstract: Methods and apparatus for defining a view path through at least one wide-angle video stream and for creation of a resultant unwarped video stream responsive to the view path. Aspects of the invention allow an operator to monitor the wide-angle video stream(s) and select which portion of the wide-angle frame to unwarp in real-time. Further, the operator can stop the playback of the wide-angle video stream and dwell within a particular wide-angle frame to create special effects such as camera tilt, pan and zoom operations in a stop action situation.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: A method is provided for watermarking FPGA configuration data. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a design file containing a marked macro received from the macro vendor, rather than the actual macro. The end user then uses an FPGA programming tool to convert the design file into configuration data. Specifically, the FPGA programming tool processes the design file to detect marked macros. If a marked macro is detected, the FPGA programming tool embeds a watermark corresponding to the macro within the configuration data.

Abstract: A method and circuit generates a complete picture from a series of digitized interlaced video fields. Each pixel in the complete picture is either duplicated from a digitized interlaced video field or interpolated from three adjoining digitized interlaced video fields. Interpolated pixels are computed from a combination of same-field and adjoining-field pixels. A percentage difference of the luminance values of the same-field and adjoining-field pixels included in the interpolation is used to maximize motion capture in the de-interlaced picture. Additional embodiments incorporate filtering of the percentage difference based on a threshold value to minimize soft noise in the de-interlaced picture.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models.

Abstract: A decoder decodes a binary input string encoded with a variable length code using an offset lookup table and a symbol lookup table. The decoder reads a first subset of leading bits from the binary input string and calculates an offset index value for the offset lookup table based on the first subset of leading bits. The offset index value is used to index the offset lookup table to obtain an offset value. Then, a symbol index value for the symbol lookup table is calculated from the offset value and a second subset of leading bits from the binary input string. The symbol index value is used to index the symbol lookup table to obtain a symbol, which corresponds to a third subset of leading bits of the binary input string.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic.blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay.