Abstract: An immersive video system for displays a view window of an environment using multiple video streams. The immersive video system includes a video source containing multiple overlapping video streams. An immersive video decoder selects an active video stream based on the location of the view window. A video decoder decodes the active video stream for the immersive video decoder. The immersive video decoder then selects the appropriate parts of the video stream to display in the view window.

Abstract: A panoramic imaging system includes multiple cameras and mirrors. The field of view of each camera is directed radially outward from a central axis of the imaging system by one of the mirrors, the target alignment planes for the mirrors being defined by a plurality of planar reference surfaces. Each mirror is mounted in a resilient mounting structure, and is held in place by the mirror contact region of a retaining structure. Each retaining structure also includes a base contact region clamped to one of the planar reference surfaces. The base contact region and the mirror contact region of each retaining structure are coplanar, so that each reflective surface is aligned with a planar reference surface. The properly directed fields of view of the plurality of cameras can be combined to form a panoramic image. According to an embodiment of the invention, the panoramic imaging system comprises an eight-sided camera.

Abstract: An environment map creation system creates an environment map from one or more images representing an environment. The environment map creation system includes a texture projection generation unit, which produces a texture projection having polygonal curved surfaces as facets. An environment map rendering unit uses the texture projection to create the environment map from the one or more images. Specifically, the environment map creation system determines an image area in the one or more images corresponding to each polygonal curved surface. The polygonal curved surface is colored based on the corresponding image area. The environment map is formed from the polygonal curved surfaces which become texels in the environment map.

Abstract: A post PLL filter is coupled to the output terminal of a phase locked loop. The post PLL filter reduces the jitter of the PLL output clock signal by increasing the Q of the phase locked loop. In addition, some embodiments of the present invention also provides amplitude magnification of the PLL output clock signal.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: An integrated-circuit using a routing ring is disclosed. The routing ring has an internal routing grid and an external routing gird. Logic circuits surrounded by the routing ring use the internal routing grid while logic circuits outside the routing ring use the external routing grid. The internal and external routing grids can use different pitches so that circuits outside the routing ring can be optimized to a first pitch. Similarly, logic circuits surrounded by the routing ring can be optimized to use a second pitch. In one embodiment, the routing ring includes a plurality of wires that connect the logic circuits surrounded by the routing ring to the logic circuits outside the routing ring.

Abstract: An immersive video display system is configured to display an immersive video formed by a plurality of compressed environment maps. The immersive video display system includes a decompression unit to partially decompress each compressed environment map to create a partially decompressed environment map. A texture rendering unit creates an image for a view window for each of the compressed environment maps by texture mapping the visible portion of a texture projection using the partially decompressed environment map. By decompressing only a portion of the compressed environment map, the immersive video display system requires less processing time to generate the contents of the view window.

Abstract: A method is provided for quickly determining low threshold voltages and high threshold voltages of a test circuit. Specifically, a transformed voltage transfer curve for the test circuit is generated. The maximum and minimum points of the transfer circuit are determined to calculate transformed voltage threshold values. The transformed voltage threshold are transformed to find the desired threshold voltages.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.

Abstract: A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.

Abstract: A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

Abstract: A system for aligning the reflective surface of a front surface mirror with a reference surface on a base structure includes a resilient support structure and a retaining structure. The front surface mirror is mounted on the resilient support structure. A contact region of the retaining structure is placed across a portion of both the reference surface and the reflective surface and is clamped to the reference surface. Because the contact region represents a coplanar portion of the retaining structure, and because the resilient support structure holds the reflective surface against the contact region, the reflective surface is aligned with the reference surface. An eight-sided camera according to the invention includes eight mirrors, each mirror being mounted in a resilient mounting structure and being clamped down by a retaining structure having a coplanar contact region spanning a reference surface and the mirror reflective surface.

Abstract: A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.

Abstract: A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

Abstract: A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.

Abstract: A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention fine tune the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.