Abstract: Multiple, single conductor, tape automated bonding (TAB) tapes are sequentially applied to a semiconductor device by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads on a semiconductor chip and to selected contacts on a lead frame followed by the laying down of at least one additional etched, single layer TAB tape which is then bonded to an inner row of bonding pads on the semiconductor chip and to different selected lead frame contacts. If desired the subsequent TAB tape may be adhered to the preceding TAB tape to increase the mechanical strength of all the tapes and improve the electrical characteristics of the tapes. The application of one or more ground planes to the assembly is also shown.

Abstract: This is related to a logic circuit which requires a double clocking latch during testing of the circuit to prevent race or flushing of the scan rings from occuring during the test mode and yet can be operated to capture and hold output data during the operation mode with stable data inputs. The preferred embodiment is a programmable latching circuit comprising a double ended cross coupled circuit having an input and an output and having first and second programmable legs and a third non-programmable leg with the first programmable leg cross coupled to the third leg and the second programmable leg being switchably cross coupled to the third leg.

Abstract: A process for the evaporation deposition of a layer of metal on a workpiece is described in which a charge of a metal is placed in a crucible formed of a material having a vapor pressure lower than the vapor pressure of the metal at a selected temperature, a shield is placed between the workpiece and the crucible, and the crucible is then heated to a first temperature sufficient to melt said charge, but insufficient to cause substantial evaporation of said charge following which the crucible is heated to a second temperature level for a time sufficient to fractionally distill the charge and sublime or vaporize any non-metallic contaminants in said charge and finally the crucible is heated to a third temperature sufficient to evaporate the charge at a selected rate at which time the shield is removed from between the cricuble and the workpiece to permit evaporant from the charge to coat the workpiece.

Abstract: A process is described for selective removal of unwanted metallization from the surface of a semiconductor device. The process comprises the usual deposition of a configurable image defining layer on the surface of the device upon which a suitable pad limiting metallurgy (PLM) has already been deposited. The layer is then opened over the pad limiting metallurgy using standard techniques and coated with a layer of the terminal metal. The coated device is then heated to just above the melting point of the terminal metal causing the melted metal, through surface tension to form a ball of metal on the PLM and to form small globules of metal on the surface of the layer and then permitted to cool. When cooled the layer is removed using the usual techniques. Because the coating of terminal metal is no longer a continuous layer on the surface of the mask, removal of the polymer mask can be accomplished in about one-tenth of the time required when compared to a deposited terminal metal layer that is not melted.

Abstract: The present invention is directed to a packaged semiconductor chip which effectively dissipates heat and has improved performance. The packaged chip has a plurality of lead frame conductors extending through the encapsulating material which are adhesively joined to the semiconductor chip, preferably by means of an alpha barrier. The conductors cover a substantial portion of the surface of the chip and thereby serve as conduits for the dissipation of heat from the chip. Wires are bonded to the conductors and extend from the conductors to the terminals on the semiconductor chip. In a preferred embodiment the semiconductor chip terminals are located along a center line of the chip. This allows for short connecting wires which in turn contribute to faster chip response.

Abstract: This is a one of the many differential multiplier circuits providing a fast selection of a one set of differential input signals from a multiplexity of differential input signals in which a plurality of differential input circuits coupled to differential outputs can be selectively prevented from being propagated to the differential outputs by activating one or more switching circuits coupled to the differential output circuits.

Abstract: An evaporation source for RF heated evaporators in which the crucible has a susceptor made of a solid block of graphite carbon having a volume commensurate with the volume of molten material prior to evaporation. Moreover, the crucible has a depth that is less than twice its diameter. These features enhance the self-fractionation of the molten material prior to evaporation to thus enhance the properties of the film as-deposited.

Abstract: A method of planarizing or smoothing the surface of a ceramic substrate by deposition of a silicon nitride layer. The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planarization with silicon nitride in accordance with the method of the present invention are sintered oxide particles which are bonded with a silicon bonding phase. The silicon content of the silicon bonding phase is greater than the silicon content of the aggregate of the oxide particles. The silicon nitride is preferably deposited by plasma enhanced chemical vapor deposition, and the silicon bonding phase is preferably a glass.

Abstract: The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the applied clock signal control the decode circuit, but the output of the latch will also control the decode circuit thus assuring the output of the decode circuit becomes latched into the set by the input clock signal.

Abstract: This is an apparatus for and a method of measuring the time coherence of high frequency signals fed into different points along a high frequency transmission line regardless of where the input signal enters the line or what the propagation delay of the line is.This describes a method and apparatus for measuring multiple unknown signals from different signal sources coupled into different points on a transmission line, which measurement is independent of the physical distances between the signal sources and the measurement device and of the propagation delay. In essence, any transmission medium positioned between the signal source and the measurement device becomes effectively transparent. This means that there is minimal signal loss and no phase change or propagation delay change due to physical position is realized. Thus, significant advantages are realized from the present invention.

Abstract: An amplifier circuit having offset voltage and offset voltage drift corrections which does not require resistive feedback and is suitable for use with unmatched high frequency field effect transistor circuits. The described circuit cancels the offset voltage of a signal amplifier and comprises means for applying differential voltages to an operational amplifier, together with a switchable feedback connecting the output of the amplifier to one of its inputs and a capacitor coupled between the feedback input of the amplifier, and one of the differential voltages. This allows amplifying of low level AC signals while reducing the error introduced by the offset voltage or the offset voltage drift of the amplifier.

Abstract: This describes an open detector circuit essentially composed of comparator circuits with their outputs coupled to each other and to an open collector driver stage, driven from the output of the comparators. The detector circuit compares the voltages, such as may be present on twisted wire pairs, connected to its line inputs to set a predetermined line voltage output. If any of the input lines connected to the detector circuit becomes open the detector circuit is held in a specified state indicating such opening until it is actively reset. The detector circuit can detect and compare both positive and negative voltages with respect to different voltage sources.

Abstract: A tester for logic circuits provided with a fast recovery power supply for supplying high current to a logic circuit under test and for measuring a low current of the circuit under test. The power supply of the tester has first and second amplifiers coupled to the CMOS circuit being tested and having dual feedback loops with one loop controlling the resistance of the other loop. The first amplifier is coupled between a reference voltage and a capacitor supplying current to the CMOS circuit under test. The second amplifier is coupled between the same reference voltage, and the output of the first amplifier. A resistive feedback is coupled between the circuit under test and the output of the first amplifier and an AC coupled impedance switching means is coupled between the output of the second amplifier and across the resistive feedback whereby the impedance switch can alter the impedance of the resistive feedback by shunting the resistor to recharge the capacitor supplying current to the circuit under test.

Abstract: This teaches a method and device for testing of the surface of a transparent object such as a photolithographic mask in which respective recordings with darkfield reflection illumination and darkfield transmission illumination is made, and the intensities measured are compared to form a different image, in which defects are characterized by high local levels of light intensity. Both recordings can be generated in a point-by-point mode if the surface is scanned by a focussed laser beam. In another embodiment, two recordings of the entire surface are digitized, and examined arithmetically for local image differences. Surfaces of opaque bodies can also be examined with the difference image of two darkfield reflection recordings made at different angles of illumination.

Abstract: A method of planarizing or smoothing the surface of a ceramic substrate by deposition of a silicon nitride layer. The silicon nitride in addition to planarizing the surface forms an alpha particle barrier. The substrates suitable for planarization with silicon nitride in accordance with the method of the present invention are sintered oxide particles which are bonded with a silicon bonding phase. The silicon content of the silicon bonding phase is greater than the silicon content of the aggregate of the oxide particles. The silicon nitride is preferably deposited by plasma enhanced chemical vapor deposition, and the silicon bonding phase is preferably a glass.

Abstract: The present invention is directed to a method of and and apparatus for continuously generating desired pulses during assumed successive desired pulse intervals with a very high time resolution by digitally predetermining the time values related to the start of the desired pulse intervals. These time values are divided into coarse and fine time rasters and coarse pulse intervals are generated from the assumed desired pulse intervals. The coarse pulses in the coarse time raster are generated from the desired pulses and each coarse pulse start and coarse pulse end, respectively is associated with a coarse pulse correction value. By adding the coarse pulse interval correction value to the coarse pulse correction value for the start and the end of the coarse pulse, respectively, a sum correction value is obtained and divided into a partial value associated with the fine time raster. The partial value of the sum correction value is used as a control value for a selected time delay for the coarse pulse edge shifted.

Abstract: The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are altered, i.e., inhibited from reading the output data of the higher order bit lines and forced to read or copy the lowest order bit lines having the same address as the uninhibited word decoder.

Abstract: This teaches that logic circuits such as Cascode circuits can be D.C. tested for normally untestable defects, such as emitter shorts or collector opens, by applying to the output of the circuit, or portion of the circuit, under test an additional voltage though an impedance. The specific embodiment teaches a resistor and diode in series as the impedence.

Abstract: The invention described avoids all the problems of the above described prior art techniques and is characterized by holding the workpiece in an inverted position, contacting the inverted face of the workpiece with a precisely metered amount of a flowable material and rotating the workpiece in its inverted position after it has contacted the polymer to coat the workpiece with a thin, uniform layer of the flowable material. The present invention is also directed to an apparatus for coating a substrate comprising, a spindle holding the workpiece in an inverted manner so that the face of the workpiece to be coated faces downwardly towards a liquid deposit of the coating material which is supported on a nozzle beneath the spindle, which spindle may be moved to permit the inverted slice to contact the liquid deposit and means for spinning the spindle in the inverted position to spread the coating material uniformly across the face of the spinning workpiece.

Abstract: An apparatus and method for testing transmission masks for corpuscular lithography, in which an image of a portion of mask is guided across a pinhole diaphragm, comprising at least one aperture with submicron dimensions, by inclining the corpuscular beam. The relative spacing of two measuring points is derived from the interferometrically measured table displacement and the beam inclination. This test for geometrical errors is effected by placing below the single hold in the diaphragm a scintillator followed by a photomultiplier coupled to an output circuit.For testing the entire mask area for errors and impurity particles, a multihole diaphragm, having submicron apertures arranged in matrix fashion, can be used above an integrated circuit of the charge transfer type which provides a MOS capacitor as a particle detector underneath each diaphragm opening. The exposure mask is scanned in steps, effecting several single exposures at each position by inclining the beam.