Abstract: The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected one of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are disabled and the output data of the highest order bit lines is transferred onto all of the lower order bit lines having the same address as the uninhibited word decoder.

Abstract: A conveying system for pneumatically conveying fragile, light weight workpieces by timed pulses of compressed air. Each pulse of air is used to propel a workpiece along a path that leads into a downwardly sloping chute and to decelerate the workpiece after it travels a selected distance down the chute so that all the initial momentum given the workpiece by the pulse of air is removed such that the workpiece will continue down the chute only under the influence of gravity. By decelerating or retarding the propelled workpiece it is prevented from impacting against queued workpieces, that proceeded it down the chute, with a high velocity that can cause breaking, chipping or jamming of the workpieces.

Abstract: A circuit arrangement is described with a sense latch for increasing the number of dynamic FET storage cells on bit lines (BL) connected to this sense latch (SL). The storage cells proper are arranged in a semiconductor structure having a diffusion layer acting as a conductor and a multiple metal layer. The outputs of the sense latch (SL) are connected to two pairs of cross-coupled charge storge elements (BB) acting as bit line coupling transistors which are connected to extended partitioned bit line pairs (BL1, BL1', and BL2, BL2'). Each section has its own reference cells and is coupled to the sense latch (SL), the sections furthest from the sense latch are coupled through low-capacity metal lines, and charge coupling elements (BB). These metal sections of the bit lines meander over the surface of the semiconductor structure.

Abstract: The present invention is especially directed towards an improved means for comparing the address inputs of word decoders in a memory array such that, when a compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder. The comparator circuit employs a ripple effect and comprises a plurality of exclusive-OR circuits interposed with a source follower circuit. The first and last steps of the comparator is an exclusive-OR circuit. The comparator circuit is extendable to any size system and result in better power performance as well as a smaller size.

Abstract: A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.

Abstract: The present invention is especially directed toward a memory cell designed for use in a register stack in which multiple independent and parallel read/write and read operations may proceed simultaneously. The cell comprises multiple write transistors and multiple read transistors all coupled to a single dynamic storage means which can be written into and read from, simultaneously.

Abstract: The present invention is especially directed towards a memory array which utilizes means for comparing the address inputs of word decoders in the system such that, when a compare occurs, selected ones of the word decoders are disabled to prevent a multiple read and selected higher order read heads are inhibited while switching the output data onto all of the output lines having the same address as the uninhibited word decoder.

Abstract: This invention concerns a method of characterizing the reliability in bipolar semiconductor devices having reliability detracting leakage current due to a parasitic FET transistor between the p-type isolation (source) and base regions (drain) of the bipolar, NPN transistor. The source of this PNP parasitic FET transistor, i.e., the isolation region and the gate are provided with electrodes and the drain region and gate electrodes short-circuited. Then, a reliability function R is determined as equal to the product N.sub.SS .times.N.sub.eff .times.N.sub.D 1/2, wherein N.sub.SS, is the interface charge density, N.sub.eff, is the oxide charge density, and N.sub.D, is the impurity concentration in the epitaxial layer. This function is correlated with the time-to-fail, such as, for instance, T.sub.50. It suffices to characterize the manufacturing line beforehand by plotting curve R=f(T.sub.

Abstract: An apparatus for carrying out, at frame rates, entity detection and verification on bit-mapped raster graphic systems by providing an entity identification bit sequence with each feature of the picture displayed. The apparatus includes a display coupled to a store for input data, serially sending items of data to the display, together with means for identifying the items of data so supplied, such that all the items of data forming a selected feature, i.e., line, circle, background or etc. of the display can be identified, and stored. Comparison and register means are used to drive a modulating means to verify the display of the items of data, forming the selected feature, when a correlation occurs between the selected feature and the feature formed by the items of data sent from the store. Verification may be emphasizing, i.e., brightening, flashing, color change, etc. the feature selected.

Abstract: An improved reactive ion plasma etching apparatus having an improved electrode, for holding the product, such as a semiconductor wafer, to be etched, provided with a plurality of apertures into which different tailored product holders are inserted so as to alter the plasma over each holder and provide more uniform etching of the product in the holder regardless of its position on the electrode.

Abstract: This describes a tristate driver circuit designed such that it will not be destroyed by excessive high voltage conditions when two such drivers are connected to a bus at the same time. The circuit accomplishes this with parallel high current, low impedance and low current, high impedance output devices, coupled to means for causing the high current, low impedance devices to supply, to the circuit output, only the initial high currents required without inhibiting the low current, high impedance devices from maintaining the steady state conditions needed to clamp the output at the desired output level. The circuit is arranged to cause both high and low current output devices to be initially conductive to charge the output terminal to the desired level, but to subsequently shut off the high current, low impedance device while keeping the low current, high impedance device in a condition to clamp the output at the desired level.

Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

Abstract: An optical bus arrangement is disclosed for interconnecting a plurality of circuit modules (15, 17 . . . ). It comprises a plurality of optical busses (25) each including a feeder waveguide (41) and a signal waveguide (43). Junctions (45) for controllably switching light from feeder to signal waveguide, and leaky regions (47) for detecting the status of the signal waveguide, are provided at regular intervals. Arrays of lasers/LEDs (33) at both ends constantly furnish light to the feeder waveguides.Each module has a plurality of input ports (27) each comprising a photodetector for detecting light from one leaky region, and a plurality of output ports (45) each comprising an electrode grating for controlling switching of light in one junction. Input ports and output ports are integrated portions of the chips. Thus, the optical waveguide switches disclosed have the specific feature of being partially incorporated as waveguide junction in a substrate (23), and partially as control electrodes integrated on a chip.

Abstract: This teaches a method of testing normally untestable, programmable integrated circuits before they are irreversibly programmed by providing the circuit with first and second impedances which combine to form an initial resultant impedance. The second of these impedances has a significantly higher level of impedance then does the first. The first of these impedances is required for testing purposes only and must be subsequently effectively removed from the circuit once testing of the circuit is completed. Once the circuit has been tested the second or higher impedance is made to interact with the circuit and functionally eliminate the first impedance from the circuit. The resultant impedance of the circuit after the first impedance has been functionally removed from the circuit can be either higher or lower than the pre-programmed initial resultant impedance of the circuit.

Abstract: This describes a method for electrically evaluating the overlay error of a photolithographic tool. In this process a reusable substrate bearing a fixed reference mark has a photolithographic tool defined metal liftoff pattern formed thereon to provide a pair of conductive lines by measuring the relative resistance of the lines with respect to one another the alignment of the tool defined pattern with regard to the reference mark may be determined and thus the overlay error of the tool established.The reference mask is formed of an L-shaped recess in a substrate so that when a metal structure is deposited on the surface of the substrate across the mask it will be made discontinuous by the mark.

Abstract: The present invention describes conformable masking techniques which can be successfully made and used in a practical manufacturing environment while providing increased resolution of photolithographic images while eliminating all manner of defects that might presently be encountered in the masks currently used in the semiconductor industry.In the present invention a body is first coated with a positive photoresist overcoated with a conformable mask which is exposed through a fixed mask and developed to define a replica of the fixed mask, together with all its defects. The underlying photoresist is then exposed to light through developed openings in the conformable mask. The conformable mask is then stripped and a new conformable mask laid down. This new conformable mask is now exposed through a second fixed mask having the same image as the first fixed mask, but presumably with different defects and developed to define a replica of the second mask.

Abstract: A method for marking a mask set to insure minimum mismatch between the masks when they are assembled into a set. Each mask in the set is evaluated against a known fixed standard, identified and marked such that when the set is assembled and utilized to produce an integrated circuit minimum mismatch between each element in each mask in the set will be realized.

Abstract: This teaches that by measuring the rate of change in gate current of an insulating gate field effect transistor, under normal operating conditions, the time required to achieve a predetermined change in source-to-drain current in the transistor can be found. Because changes in gate current depends more on sensitivity on charge trapping in the oxide than do changes in channel current, and since the gate current occurs only in the small region of electron emission, the effects on gate current are more quickly developed than the secondary effect of reduced channel current due to the charge in gate oxide caused by the presence of trapped electrons.

Abstract: A method for annealing ion implanted regions buried in a semiconductor substrate without the undesirable effects of thermal diffusion which includes the radiation of the substrate by a continuous laser having an emission frequency longer than 600 nanometers which the buried ion implanted regions will absorb strongly but which will be substantially unabsorbed by the unimplanted regions.Superior results can be obtained when the substrate is heated to approximately 300.degree. during this laser annealing.

Abstract: This describes different methods of using a single photoresist layer to define both metal contact vias and metal lift-off areas on semiconductor integrated circuits. The methods use positive photoresist containing a small amount of base such as imidazole to provide a lift-off overhang when the resist is exposed and developed to provide a reversal image.