Abstract: New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the second frequency band. The new version devices may operate on a first carrier frequency (within the first frequency band) while old version devices may operate at a second carrier frequency (within the second frequency band). The new version devices and/or the old version devices may also support carrier-less modulations. Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The payload of the new version signal may be formed in the same manner or may be formed in have a wider bandwidth, higher data rate format.

Abstract: An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles during the timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in pattern memory for the timed test pattern. The method and apparatus of the present invention can be implemented to test integrated circuits comprising circuitry operating in first and second time domains wherein the first and second timing intervals of the timed test pattern correspond to the first and second time domains of the circuit, respectively.

Abstract: Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.

Abstract: 16 QAM (Quadrature Amplitude Modulation) and 16 APSK (Asymmetric Phase Shift Keying) TTCM (Turbo Trellis Coded Modulation) with minimum bandwidth efficiency of 3 bit/s/Hz (bits per second per Hertz) using a rate 2/4 constituent encoder. Various encoder designs are presented that are operable to generate a signal whose modulation may vary as frequently as on a symbol by symbol basis while providing relatively very high throughput. Rate control sequences including RCs (Rate Controls), arranged in a period, govern the manner in which symbols of a signal are generated. The RCs correspond to various modulations that may each have a unique constellation and corresponding mapping. Different RCs may be included within a rate control sequence that correspond to 16 QAM, 16 APSK, QPSK (Quadrature Phase Shift Key), or even other modulation types. In addition, 1 or more uncoded bits may be used to generate the symbols of the coded signal.

Abstract: A method for selectable quantization for use in an encoder for compressing video and/or audio data includes processing that begins by receiving discrete cosine transform data of an encoded signal. The processing continues by obtaining a quantization table. The processing then continues by obtaining a plurality of scaling factors. The process then continues by generating a plurality of quantized value sets of the discrete cosine transform data based on the quantization table and the plurality of quantization scaling factors. The resulting data is then multiplied separately by each of the quantization scaling factors to produce the plurality of quantized values sets. The process then continues by selecting one of the plurality of quantized value sets based on quantization selection criteria.

Abstract: A method and apparatus for signal gain adjustment within an RF integrated circuit (IC) include processing that begins by determining the signal strength of a received RF input signal with respect to a first signal strength scale to produce a signal strength indication. The processing continues by determining whether the signal strength indication exceeds a first high power threshold. If not, the receiver continues to process received RF signals without additional attenuation. If, however, the signal strength indication exceeds the first high power threshold, the received RF input signal is attenuated to produce an attenuated RF input signal. In addition, the first signal strength scale is shifted to produce a shifted signal strength scale. The processing continues by determining whether the signal strength of the attenuated RF input signal exceeds a high power threshold of the shifted signal strength scale or is below a low power threshold of the shifted signal strength scale.

Abstract: A modem includes a Digital Access Arrangement (DAA) Circuit and modem software that is executed by a processor. When the DAA Circuit detects that the modem software is nonfunctional, it enters an on-hook state to prevent blocking of a coupled telephone line. A nonfunctional state of the modem software is detected when the modem software ceases to interact with the DAA Circuit in an expected manner. In a first operation, the nonfunctional state is determined when the modem software does not reset a count down timer in the DAA Circuit before the count down timer reaches a termination value. In a second operation, the nonfunctional state is determined when the modem software does not access the DAA Circuit before the count down timer reaches the termination value. In a third operation, the nonfunctional state is determined when the modem software ceases writing transmit data to DMA memory.

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: A method for current limiting of an output of a DC-to-DC converter begins by determining a current loading duty cycle of the output of the DC-to-DC converter (i.e., the present duty cycle given the loading of on the output). The processing then continues by comparing the current loading duty cycle with a zero loading duty cycle of the output (i.e., the duty cycle when the output has no load). The processing continues by limiting duty cycle of the output to the zero loading duty cycle plus a duty cycle loading offset when the current loading duty cycle exceeds the zero loading duty cycle plus the duty cycle loading offset.

Abstract: A single integrated circuit includes logic that supports 10BASE-T, 100BASE-T and 1000BASE-T transceiver functionality. The invention implements power management techniques by placing unused functionality in sleep mode. When the functionality is required later, then that functionality may be awakened again and used as required for the particular situation. A processor is able to interact with the media access controller (MAC), and the MAC then communicates with the physical layer (PHY). The invention is adaptable to various devices that are capable to operating using 10BASE-T, 100BASE-T and 1000BASE-T, even those the PHY of these devices may be somewhat different.

Abstract: A method and apparatus for controlling the amount of quantization processing used within an encoder that compresses video and/or audio data include processing that begins by receiving discrete cosine transform data of a block of a frame of data. The process then proceeds by obtaining a quantization table related to the frame of data. The processing then continues by obtaining a quantization scaling factor related to the frame. The processing then continues by determining whether quantization processing limits have been exceeded for quantization of preceding blocks of the frame of data. If the number of bits processed for the preceding blocks exceeds a certain desired level, the processing increases the quantization scaling factor. The processing then continues by generating quantization data from the discrete cosine transform data, the quantization table and the increased quantization scaling factor.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An on-chip differential inductor includes a 1st interwound winding having a substantially octagonal shape, or rectangular octagonal shape, and a 2nd interwound winding having a substantially octagonal shape, or rectangular octagonal shape, that is interwound with the 1st interwound winding. Both the 1st and 2nd interwound windings are on the same layer of the integrated circuit. Each interwound winding includes two nodes; one of node of each winding is commonly coupled to a reference potential. The other node of each winding is operably coupled to receive a respective leg of a differential signal.

Abstract: A low power supply band-gap current reference includes a 1st P-N junction device, a 2nd and P-N junction device, a 1st current source, a 2nd current source, a 1st resistor, a 2nd resistor, a 3rd resistor, an operational amplifier, and a current mirror. The 1st and 2nd P-N junction devices are operably coupled to the 1st and 2nd current sources, respectively. The 2nd P-N junction device is a larger device than the 1st P-N junction device. The 2nd resistor is operably coupled in parallel with the 1st P-N junction device and the 2nd resistor is coupled in series with the 2nd P-N junction device. The 3rd resistor is coupled in parallel with the series combination of the 2nd resistor and 2nd P-N junction device. The operational amplifier is coupled to control the 1st and 2nd current sources based on the voltage imposed across the 1st and 2nd resistors. The current mirror is operably coupled to mirror the current of the 1st and/or 2nd current source to provide a band-gap reference current.

Abstract: A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: A printed dipole antenna includes a metal trace having first type sections and second type sections, wherein currents within the first type sections substantially cancel and currents the second type sections are substantially cumulative.

Abstract: A method for conserving power begins by measuring processing speed of at least a portion of an integrated circuit (IC) to produce measured processing speed. The portion of the IC may be a test circuit, a critical path of the IC, and/or a replica of the critical path of the IC. The processing continues by comparing the measured processing speed with a critical processing speed for the at least a portion of the integrated circuit. The processing then continues by adjusting supply voltage to the integrated circuit to reduce power consumption of the integrated circuit when the measured processing speed compares favorably to the critical processing speed.

Abstract: A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes a phase equalizer, an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The phase equalizer receives a modulated baseband signal and phase equalizes the modulated baseband signal to produce a phase equalized modulated baseband signal. The IF modulator receives the phase equalized modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope.