Abstract: A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives the digital data and interpolates and filters the digital data to produce an interpolated and filtered digital signal. The modulator receives the interpolated and filtered digital signal and a feedback signal. The modulator modulates the interpolated and filtered digital signal based upon the feedback signal to produce a modulated signal at a modulator clock rate. The time dither clock reduction circuit receives the modulated signal and applies both clock reduction and time dithering to the modulated signal to produce a time dithered/clock reduced modulated signal. The time dithered/clock reduced modulated signal serves as the analog signal and also serves as the feedback signal.

Abstract: An amplifier circuit uses low threshold voltage devices for mid rail response in low voltage applications, but uses a high threshold voltage device at an output stage of the amplifier to generate an output from the amplifier.

Abstract: Efficient design to calculate extrinsic information for Soft-In-Soft-Out (SISO) decoder. A design provides for very efficient performing extrinsic value calculation when performing iterative decoding. The design also accommodates a variety of rate controls each having varying bandwidth efficiencies. By grouping and capitalizing on the commonality of many of the intermediate terms that are employed when calculating the extrinsic values needed to perform iterative decoding, a great saving in terms of hardware may be achieved. In addition, this also provides a great deal of improvement in terms of operational speed and overall decoder system efficiency. The design is also adaptable to assist in performing decoding input symbols having multiple bits; a single design may be employed to accommodate different input symbols that have different numbers of bits. The extrinsic calculation employs min* processing in one embodiment; however, the design may also be performed using max*, min, or max processing.

Abstract: A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

Abstract: A system for delivering SMS messages to a mobile terminal includes an apparatus and method that deliver the SMS messages either using legacy SMS message formats or data packet formats. Additionally, a connection is created between a message center and a gateway GPRS support node wherein SMS messages may be transmitted to the gateway GPRS support node in a data packet format. To provide this capability, the gateway GPRS support node includes a unique port address for receiving SMS messages and circuitry for processing SMS messages received in a data packet format. A serving GPRS support node is formed to include circuitry for determining whether to transmit the SMS message to the mobile terminal in a data packet format or in a legacy SMS message format.

Abstract: A system for delivering SMS messages to a mobile terminal includes an apparatus and method that deliver the SMS messages either using legacy SMS message formats or data packet formats. Additionally, a connection is created between a message center and a gateway GPRS support node wherein SMS messages may be transmitted to the gateway GPRS support node in a data packet format. To provide this capability, the gateway GPRS support node includes a unique port address for receiving SMS messages and circuitry for processing SMS messages received in a data packet format. A serving GPRS support node is formed to include circuitry for determining whether to transmit the SMS message to the mobile terminal in a data packet format or in a legacy SMS message format.

Abstract: Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem, e.g., the Kalman gain solution to the RLS problem. A fast recursive method, e.g., fast transversal filter (FTF) technique, for computing the Kalman gain is then directly used to compute Feed Forward Equalizer (FFE) coefficients gopt. The complexity of a conventional FTF algorithm is reduced to one third of its original complexity by choosing the length of a Feed Back Equalizer (FBE) coefficients bopt (of the DFE) to force the FTF algorithm to use a lower triangular matrix. The FBE coefficients bopt are then computed by convolving the FFE coefficients gopt with the channel impulse response h. In performing this operation, a convolution matrix that characterizes the channel impulse response h extended to a bigger circulant matrix.

Abstract: An inventive method and apparatus includes a network of servers for providing information on a push basis to a user or consumer that desires to receive event driven information according to specified conditions. The types of push information include event driven information services as well as very targeted advertisements. An information server receives location information that identifies the specific location or Picocell within which the consumer mobile terminal has traveled. Then, a consumer profile is transmitted to vendors proximate to the mobile terminal location as a part of determining whether to transmit information or advertisements to the consumer. If the consumer profile specifies solicited advertisements only, advertisements may only be sent if they include products or services as identified in the consumer profile information.

Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF from end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor operably couples to the RF front end, is operable to receive the baseband signals, is operable to pre-equalization process the baseband signals to produce processed baseband signals, and is operable to post-equalization process soft decisions. The equalizer module operably couples to the baseband processor and is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.

Abstract: A variable gain amplifier includes circuit elements that may be partially powered down during transmit modes of operation and that may be powered back up whenever the radio transceiver receives a data packet within a specified settle time even for high throughput RF communications. The radio transceiver circuit may be powered down even in high throughput communications during a transmit mode to reduce power consumption. A DC offset cancellation block is operably coupled to the variable gain block to substantially remove any DC offset from the amplified output. The variable gain amplifier is further able to provide DC offset cancellation within the required settle time by holding the offset value during a dormant mode of operation.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A radio receiver portion of a transceiver includes a differential amplifier that is used to provide a fast response. A pair of input MOSFETs of the differential amplifier stage are coupled to an active load. A voltage follower circuit is coupled to each output stage of the two stage differential amplifier to drive a current through a load without reducing the output voltage. The voltage follower stages each include a current mirror that replicates current level defined by an input MOSFET of the voltage follower circuit and, by its configuration, a voltage level produced by the differential amplifier to the input MOSFET of the voltage follower circuit. Accordingly, the differential amplifier stage defines the amplification of the circuit while the voltage follower circuits replicate the amplified output with the ability to drive a load.

Abstract: A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) in a radio receiver to provide a plurality of gain steps thereby providing automatic gain control (AGC) in a receiver intermediate frequency (IF) stage comprises an analogy peak detector formed to including a constant current source and a plurality of MOSFETs all configured to produce an output voltage (DC) whose value reflects a peak amplitude of a received differential quadrature phase shift keyed (QPSK) signal. A first circuit portion generates currents that are proportional to the square of the magnitude of the gate to source voltage for each of a plurality of MOSFETs coupled to receive the differential QPSK signal and a second circuit portion produces a voltage that is equal to the square root of the sum of the squares of the currents produced (drawn) by the MOSFETs of the first circuit portion.

Abstract: A complex filter such as the channel select filter in a radio transceiver is implemented using a transconductance/C topology to benefit from the ability to tune such filters and thereby stabilize the output transfer function of the filter over variations in temperature, power supply voltage and process. The topology is based on an active R/C biquadratic topology to achieve the additional benefit of independently controlled stages. The problem created by the R in the output impedance is can be overcome by separately tuning the R value along with the transconductance/C ratio, by implementing the R as a transconductance amplifier having common mode feedback, or by implementing the transconductance amplifiers of the topology using Nauta transconductors, and unbalancing the common mode circuit of the Nauta transconductor to achieve a differential resistance that can be used to implement the R in the output impedance.

Abstract: A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon which the semi conductive die resides, a plurality of package pins, a plurality of bond wires, a downbond rail, and a plurality of downbonds. Each of the bond wires couples between a corresponding die pad and a corresponding package pin. The downbond rail couples to the heat slug. At least one downbond couples between a die pad corresponding to the first portion of the RF circuit and a respective location on the downbond rail, serves as an inductor for a second portion of the RF circuit, may include a plurality of downbonds coupled in parallel, and has a length and/or a diameter selected to provide a desired inductance.

Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.