Abstract: A projected artificial magnetic mirror (PAMM) radar device includes a transceiver module, a shaping module, and an antenna structure. The antenna structure includes a plurality of metal patches, a metal backing, a dielectric material, and one or more antennas. The metal patches are electrically coupled to the metal backing to form an inductive-capacitive network that, for the one or more antennas and within a given frequency band, substantially reduces surface waves to obtain a detectable angle of incidence of approximately ninety degrees.

Abstract: A digital rights management (DRM) node module for use in a node of a public data includes a node data module that stores DRM data associated with a plurality of digital files, the DRM data including a plurality of DRM identifiers. A packet monitoring module receives the plurality of DRM identifiers from the node data module, that receives packets containing incoming content and compares the incoming content to the DRM identifier, and generates event data when the incoming content matches at least one of the DRM identifiers. A node reporting module receives the event data, and generates node report data based on the event data.

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, it is processed to produce a null page pattern. The wireless terminal may then enter a sleep mode or reduced functionality mode for a predetermined period of time. The wireless terminal awakes from the sleep mode to receive additional encoded paging bursts. Processing the additional encoded paging bursts produces a processed encoded paging burst, which is compared to the null page pattern. When compared favorably, the encoded paging burst is considered a null page, allowing the wireless terminal to re-enter the sleep mode without fully decoding the paging burst.

Abstract: Transmitter calibration of a wireless device is initiated based upon an operational value of the wireless device. The calibration operations are performed over a plurality of calibration time periods, each calibration time period divided into a plurality of first interval portions interspersed with a plurality of second interval portions, for each calibration time period of the plurality of calibration time periods, respective calibration settings are applied. During the first interval portions substantially fixed first current input is applied to at least one gain adjustable element of the RF circuitry. During the second interval portions, varying current input is applied to the at least one gain adjustable element of the RF circuitry. Output levels of the RF circuitry are measured over the calibration time period. Operational calibration settings for the baseband processing circuitry and analog signal path components of the transmitter are selected based upon the calibration operations.

Abstract: A method to process DP bits within a WCDMA receiver where a noise estimation that may be implemented within hardware is provided for improved flexibility and performance. DPCH pilot symbols are received, quantized, channel compensated and combined. The computation of an SNR estimate based on the combined DPCH pilot symbols is provided. Noise estimation is used as part of the SNR estimation of the DP bits (used for downlink power control). This method does not rely on the assumption that the channel is constant over the DP field, while prior methods did.

Abstract: An integrated circuit radio transceiver and method therefor includes an integrated circuit radio transceiver operable to provide pre-distortion settings that correspond to specified analog transmit path gain levels. Further, a change in gain is provided solely through digital gain when the new gain is within a specified range. If the gain change is not within the specified range, the gain is provided by a new transmit path gain module and, if necessary, with additional digital gain. Additionally, a new pre-distortion setting is applied to correspond to the new analog transmit path gain setting.

Abstract: A programmable antenna assembly includes a configurable antenna structure, a configurable antenna interface, and a control module. The configurable antenna structure includes a plurality of antenna elements that, in response to an antenna configuration signal, are configured elements into at least one antenna. The configurable antenna interface module is coupled to the at least one antenna and, based on an antenna interface control signal, provides at least one of an impedance matching circuit and a bandpass filter. The control module is coupled to generate the antenna configuration signal and the antenna interface control signal in accordance with a first frequency band and a second frequency band such that the at least one antenna facilitates at least one of transmitting and receiving a first RF signal within the first frequency band and facilitates at least one of transmitting and receiving a second RF signal within the second frequency band.

Abstract: Analog signal paths are utilized between a baseband processor and a radio front end to support high throughput communications for a multiple in multiple out radio transceiver that support communications over two or more antennas. Specifically, analog differential I and Q path communication signals are exchanged between a radio front end core and a baseband processor to maximize throughput capacity for high data rate signals. Along the same lines, the impedances of traces and the interface are matched to reduce I/Q imbalance.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract: Communications signal transcoder. A solution is provided to transcode a signal from a first signal type to a second signal type to ensure proper interfacing between devices that may operate using different signal types. For example, within a communication system, a first signal type (having a first modulation type, e.g., 8 PSK) may be received. The transcoder then ensures that this signal, after it has undergone any initial processing (such as tuning, down-converting, decoding, and so on), is encoded into a second signal type (having a second modulation type, e.g., QPSK) such that it can interface properly with a device for which the received signal is intended. This transcoder functionality may be implemented within discrete components, or it may alternatively be integrated within a functional block of an integrated circuit. This functionality may be implemented in a variety of communication systems including satellite, cable television, Internet, and others.

Abstract: A multiple frequency antenna array includes a first antenna circuit and a second antenna circuit. The first antenna circuit has a first radiation pattern and is tuned to a first carrier frequency. The first antenna circuit transmits a first representation of a radio frequency (RF) signal at the first carrier frequency, where the first carrier frequency corresponds to a carrier frequency of the RF signal and a first frequency offset. The second antenna circuit has a second radiation pattern and is tuned to a second carrier frequency. The second antenna circuit transmits a second representation of the RF signal at the second carrier frequency, where the second carrier frequency corresponds to the carrier frequency of the RF signal and a second frequency offset.

Abstract: An integrated circuit (IC) includes an RF section, a DSP, and a plurality of processors. The RF section and the DSP process an inbound RF signal to produce inbound data and process outbound data to produce an outbound RF signal. In addition, the DSP converts an outbound analog audio signal into an outbound digital audio signal and converts an inbound digital audio signal into an inbound analog audio signal. A first processor converts the inbound data into the inbound digital audio signal and converts the outbound digital audio signal into the outbound data. A second processor performs a user application that includes at least one of generation of the inbound analog audio signal and generation of the outbound analog audio signal and performs an operating system algorithm to coordinate operation of the user application.

Abstract: An RF integrated circuit (IC) includes a processing module that determines a selected one of the plurality of power modes based on current use characteristics of at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and generates a plurality of power supply signals based on the power mode signal.

Abstract: A host interface module includes a millimeter wave transceiver that is coupled to wirelessly communicate read commands, write commands, read data and write data between a flash memory device and a host device over a millimeter wave communication path in accordance with a host interface protocol. A protocol conversion module is coupled to convert the read commands, the write commands and the write data from the host interface protocol and to convert the read data to the host interface protocol. A host module is coupled to decode the read commands and the write commands from the host device, to process the read commands to retrieve the read data from the flash memory and to process the write commands to write the write data to the flash memory.

Abstract: A method and apparatus is disclosed to extend a dynamic input range of an analog to digital converter (ADC). A composite ADC may include one or more ADCs. The one or more ADCs compare a signal metric of an analog input signal to quantization levels to produce intermediate digital output signals using one or more non-clipping input values. The composite ADC may select among the one or more intermediate digital output signals based on the signal metric of the analog input signal to produce a final digital output.

Abstract: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of non-null sub-matrices, then a same number of memories are employed when decoding each LDPC coded signal. However, those particular memories employed can be different subsets for when decoding each LDPC coded signal. In embodiments where each LDPC code includes a different number of non-null sub-matrices within its respective LDPC matrix, then a different number of memories are employed when decoding each LDPC coded signal. Various degrees of parallelism in decoding can also be employed in which different numbers of bit engines and check engines can be employed when decoding different LDPC coded signals.

Abstract: An integrated circuit (IC) includes a baseband processing module and a radio frequency (RF) section. The baseband processing module is coupled to convert outbound data into amplitude modulation information and phase modulation information when the IC is in a cellular data mode and to convert an outbound radio frequency identification (RFID) signal into RFID amplitude modulation information when the IC is in an RFID mode. The RF section is coupled to generate an outbound RF data signal in accordance with the amplitude modulation information and the phase modulation information when the IC is in the cellular data mode and to generate an outbound RF RFID signal in accordance with the RFID amplitude information when the IC is in the RFID mode.

Abstract: A method and apparatus in an integrated circuit radio transceiver are operable to apply a modified control signal to drive logic that includes a plurality of first devices having a first threshold voltage and a first gate oxide thickness that are both greater than a second threshold voltage and a second gate oxide thickness for a greater second plurality of devices within the integrated circuit radio transceiver. The transceiver therefore generates a first control signal having a first magnitude operable to drive logic that includes a plurality of devices having a second threshold voltage and applies the first control signal to a level shifter to produce the modified control signal.

Abstract: A power status signal is received in an integrated circuit that indicates an inductive power status of an off-chip inductive power module and a battery power status of a battery. A power mode is selected based on the at least one power status signal. A power mode signal is generated based on the selected power mode. A power supply signal is generated and adjusted in response to the power mode signal.