Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: The disclosure relates to a process station to precisely control the electrochemical anodization of specially prepared silicon substrates. Remotely placed voltage probes are utilized to monitor changes in the potential drop across the wafer as the anodization proceeds. As the available anodilizable area changes, the voltage drop across the wafer and hence the anodization current density is maintained at the desired value by the computer through the use of active feedback provided by these probes. Any desired anodization conditions can be programmed into the system using the system software, thereby adding an even greater degree of control over the process.

Abstract: Circuitry for controlling the operation of a transient voltage compensation circuit is disclosed. An input buffer circuit 10 is provided which includes a phase splitter transistor 30 having a base at which input signals are applied and an emitter which is coupled to internal ground through Schottky diode 32. A compensation circuit 12 prevents the undesirable switching of transistor 30 during fluctuations in the internal ground voltage level by drawing current from the base of transistor 30 through transistor 42 which has a base connected to a source of current and an emitter connected to internal ground. Transients in the internal ground level effect the turn on of transistor 42 which prevents the turn on of transistor 30 under low input voltage conditions. A compensation control circuit 11 is provided to disable compensation circuit 12 under high input voltage conditions yet allow its normal operation when a low voltage level is applied at the input.

Abstract: A method for making integrated circuits in which a polyimide/conductor multilevel film (17) in cast on a substrate (10), using available or existing semiconductor processing equipment. The polyimide film (17) is formed from readily available polyamic acid resins, and the conductor (16) can be sputtered aluminum formed to interconnection conductor patterns (16,16-) by standard photolithographic techniques. After fabrication of the multilayer film (17), the conductors (16,16') of the film (17) and the device circuit (30) are brought into aligned contact, and the device circuit (30) affixed to the film (17). The film (17) and the device circuit (30) are then removed from the substrate (10) for further processing, such as bonding the device and film to a mother board or leadframe, as desired.

Abstract: A signed digit adder (10) includes a plurality of cells (12) which input signals X.sub.s, X.sub.m, Y.sub.s, Y.sub.m, R.sub.-1 and U.sub.-1, where X.sub.s and X.sub.m are the sign and magnitude bits of one digit of a signed bit representation. Similarly, Y.sub.s and Y.sub.m are the sign and magnitude bits of the second operand. R.sub.-1 and U.sub.-1 are signals received from the preceding cell (12). Each cell outputs R and U bits, and the sum bits Z.sub.s and Z.sub.m. Each cell (12) comprises function blocks (14-26) which determine the outputs from the given inputs. Function block (14) determines the output R as NOT(X.sub.s +Y.sub.s). Function block (20) determines the output U=E.multidot.NOT(R.sub.-1)+NOT(E).multidot.NOT(Q) where Q=(NOT (X.sub.s)+NOT (Y.sub.s)).multidot.X.sub.m. The determination of Q is performed in function block (16). Function block (24) determines the output Z.sub.s =U.sub.-1 .multidot.T and function block (26) determines the output Z.sub.m =U.sub.-1 XOR (NOT (T)).

Abstract: A CCD imager (10) is adaptable for recording a still image and translating the still image into a NTSC television format. An image array (12) of the imager (10) has a plurality of cells arranged in rows and columns (35-37). The cells are further divided into a plurality of fields including a first field and a second field, cells in any one row belong to a single field. A memory array (16) of the imager comprises a plurality of memory cells (128, 130, 82, 84, 174, 176, 152 and 154) including first cells (128, 82, 174, 152) for storing signals from the first field, and second cells (130, 84, 176, 54) for storing signals from the second field. A transferor (14) is operable to transfer the first field signals to the first memory cells (128, 174, 152), and also transfers the second field signals to the second memory cells (130, 84, 176, 154).

Abstract: A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

Abstract: A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width.

Abstract: The disclosure relates to a method of making a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

Abstract: A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of the logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.

Abstract: A reset circuit for a CMOS memory array is disclosed wherein the voltage supply for the standard six transistor memory cell is replaced by a pair of parallel connected transistors disposed between a fixed voltage source and the memory cell. The transistors are controlled by the reset signal and are complementary in that one is n-channel and the other is p-channel. The n-channel transistor is sized to prevent excess current flow to the memory cells to prevent an excessive charge build up therein for a logical "1" representation. In addition, the n-channel transistor provides a Vtn drop thereacross to prevent current flow in the memory cells during reset.

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Abstract: A logic circuit which includes first and second differentially connected amplifying devices having first and second complementary output voltage nodes. Means for limiting the output voltage swing of the devices at the output nodes to a predetermined range reduces the required voltage supply source. A reference voltage is coupled to the second amplifying device while a plurality of input diodes are coupled in parallel to an input of the first amplifying device to form AND inputs thereto. A biasing element is coupled to the input of the first amplifying device.

Abstract: A fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first CMOS inverter having a P-channel transistor (98) and an N-channel transistor (102) and the second inverter having a P-channel transistor (90) and an N-channel transistor (96). The output of the first inverter is connected to the input of the second inverter with the output of the second inverter connected to the input of the first inverter through a pass transistor (104). The pass transistor (104) is conductive during the static mode of operation and is nonconductive during the write operation. During write, the input of the first inverter is forced to a predetermined logic state with the pass transistor (104) nonconductive. After write, the pass transistor (104) conducts and reconfigures the latch.

Abstract: A horizontal scanner (30) is formed on-chip with a sensor array (12). The scanner comprises a plurality of stages (114, 116) that preferably each have only four transistors (132, 122, 140 and 118). In one embodiment, dual sense lines (50, 52) are provided and a clocking scheme is used such that a clock signal (.phi..sub.1, .phi..sub.2) is used to address one sense line (50) while resetting the other sense line (52) by means of reset circuitry (32). The scanner (30) of the invention is adaptable to be used with imagers having electronic zooming and planning features, and is further adaptable in use for dual-line readout, three-phase (RGB) readout, and multiple-phase readout applications.

Abstract: A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).

Abstract: A mask (38), which is particularly useful in parallel-printing ion beam lithography because of its dimensional stability, is disclosed. The mask (38) represents a relatively rigid screen (22) constructed from a relatively rigid material, such as monocrystalline silicon, with meshes (28) formed through the screen (22) over the entire area of the screen (22). The preferred embodiment applies a less rigid filler material (34) into the meshes (28) over the entire area of the screen (22), then removes the filler material (34) from transmissive areas (42) of the mask (38).

Abstract: A CCD structure wherein the patterned well implant and/or patterned barrier implant geometries are modified to exploit two dimensional potential modification effects to induce potential gradation along the length of the CCD pixel. Preferably these geometry modifications are in the form of wedge-shaped extensions of the well doping into the barrier region. The modifications thus induced to the potential profile for electrons in the direction of the charge transfer along the CCD pixel mean that the regions of flat potential, wherein carrier transport is diffusion dominated, are shortened, so that charge transfer efficiency can be improved at reasonably high clock rates.

Abstract: An image sensor array (12) is comprised of a plurality of sensor elements (60) arranged in rows (62) and columns (64). Each element (60) is operable to modulate an output voltage signal responsive to charge accumulating in its gate region (70) responsive to incident light. Circuitry (74, 84, 78, 72) is provided to obtain and store a signal that is related to a threshold voltage differential produced by the accumulated charge, and not to the intrinsic threshold voltages or sizes of sensors (60). The array (12) has automatic blooming control, and can exhibit electronic iris, zooming and panning functions.

Abstract: A low 1/f noise amplifier has been provided for an output of a CCD imager. To reduce clock noise, the amplifier employs a differential detection scheme. Linear stages (54, 76) are coupled by capacitors (60, 82) to a differential amplifier (64). Differential amplifier (64) employs a first (112, 118) and a second (172, 198) differential transistor pair. The second differential pair (172, 198) is cross-coupled to the outputs of the first differential pair (112, 118) by load resistances (180, 206) with the voltage drop across them remaining substantially constant. To maintain stability, the positive and negative branches of the amplifier are periodically reset by a resetter (210). The input nodes (62, 86) are periodically reset to a voltage reference.