Abstract: A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Abstract: A system and method are provided for electrostatic discharge (ESD) protection circuit having overshoot and undershoot voltage protection during a power supply ramp-up of the circuit. In a specific embodiment, the ESD protection circuit of the present invention includes an ESD discharge circuit coupled between a power supply node and a ground supply node, a trigger circuit coupled to the ESD discharge circuit, the trigger circuit to turn the ESD discharge circuit on in the presence of a voltage spike during the power supply ramp-up and to turn the ESD discharge circuit off in the absence of a voltage spike during the power supply ramp-up, and a delay circuit coupled between the discharge circuit and the trigger circuit, the delay circuit to slow down the turn-off of the discharge circuit to prevent an overshoot or undershoot voltage condition during the power supply ramp-up of the circuit.

Abstract: A switch includes an arbiter that receives a plurality of requests from N input ports, and determines N round robin arbitration option winners by performing N round robin arbitration options on the requests, each of the N round robin arbitration options performed assuming that a different one of the N input ports was a previous round robin arbitration winner. After the actual previous round robin arbitration winner is identified, a current round robin arbitration winner from among the N round robin arbitration option winners is determined by selecting the round robin arbitration option winner in which the assumed previous round robin arbitration winner is the actual previous round robin arbitration winner.

Abstract: A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for performing symbol processing operations on the data packets. The baseband processor is scalable such that digital signal processors may be added to, or removed from, the baseband processor. Further, the baseband processor is programmable such that the symbol processing operations may be distributed among the digital signal processors.

Abstract: A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.

Abstract: A system and method are provided for a folded cascode amplifier circuit that includes a first order high-pass filter coupled to a first bias voltage, a first input signal and a second input signal, the first input signal and the second input signal defining a differential input signal and the first order high-pass filter arranged to establish a first bias output and a second bias output. To amplify the full-spectrum content of the input signal, the amplifier circuit includes a full-spectrum content amplifier coupled between the first input signal, the second input signal and a current source. To amplify the high-frequency content of the input signal to achieve equalization, the amplifier circuit includes a high-frequency content amplifier coupled to the first bias output and the second bias output, the high-frequency content amplifier arranged to amplify the high-frequency content of the differential input signal to achieve equalization.

Abstract: A packet switch arbitration system and method for arbitration in a packet switch. In one aspect, a method of issuing grants to an ingress port is disclosed in which a first grant request and burst signal are activated at an ingress port having more than one word available for transfer through the switch. A first grant is issued to the ingress port on a first interval. A subsequent grant is issued to the ingress port on a subsequent interval, where the subsequent grant is issued before the ingress port has validated the first grant request.

Abstract: A novel method and circuit are disclosed for providing an alternate function to a semiconductor device having a normal operating voltage range and an input pin for receiving an input signal of a voltage level within a normal signal voltage range, for selecting an alternate function, whose steps consist of determining, when a voltage is received at the input pin, whether the voltage is within a normal signal voltage range, enabling the performing of a primary function if the signal voltage is within a normal signal voltage range, and initiating an alternate function when the voltage is outside of the normal signal voltage range.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: In one aspect, a negative voltage coefficient resistor is provided. The negative voltage coefficient resistor includes an insulative layer positioned between a polycrystalline silicon resistive layer and a silicide layer. Upon application of an appropriate voltage bias at the silicide layer of the resistor, a tunneling current is established across the insulative layer and is supplied to the polycrystalline silicon resistive layer. The tunneling current limits the current flow through the polycrystalline silicon layer, producing a resistor having a negative voltage coefficient of resistance and a reduced temperature coefficient of resistance.

Abstract: A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a multiplexer that is enabled to select content from a base address register in an array of base address registers, a comparator enabled compare a base address in the content with a target address from a packet, and a comparator enabled to concurrently compare a limit address in the content with the target address and the output of the limit address comparator. The method includes receiving the target address, locating a matching base address in an array of base address registers, concurrently comparing the target address with a limit address associated with the matching base address, and indicating if said target address is not valid.

Abstract: A packet switch includes a packet processor for processing data packets. The packet processor receives a data packet including a data payload, identifies data portions in the data payload, and determines a destination address for each data portion. Additionally, the packet processor constructs data packets, each including a data portion and the destination address of the data portion. The packet processor then routes each of the constructed data packets based on a destination identifier of the constructed data packet. An external recipient can then store the data portions of the constructed data packets based on the data addresses in the constructed data packets.

Abstract: A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generates a charge current based on the bias voltage. The charge pump generates an output based on the charge current to maintain a constant open-loop bandwidth of the phase-lock loop.

Abstract: A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region.

Abstract: A clock generator includes a clock circuit and a voltage-controlled oscillator in a phase-locked loop. The clock circuit monitors input clock signals and selects one of the input clock signals based on characteristics of the input clock signals. The voltage-controlled oscillator generates a reference clock signal based on the selected clock signal. The clock circuit also includes synthesizers for generating clock signals, each of which has a frequency being a non-integer multiple of a frequency of the reference clock signal. Additionally, the clock circuit individually offsets the clock signals generated by the synthesizers relative to the reference clock signal. The clock generator is capable of switching the input clock signal during operation of the clock generator while maintaining the reference clock signal. Further, the clock generator is programmable to control operation of the clock circuit.

Abstract: A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.

Abstract: A clock generator generates multiple clock signals based on an input signal and adjusts the phases of the clock signals relative to a phase of the input signal, based on a control signal. The clock generator includes a phase locked loop that includes a phase shift unit. The phase shift unit selects some of the clock signals based on the control signal and generates a feedback signal based on the selected clock signals. The feedback signal has a phase based on the phases of the selected clock signals. The phase locked loop aligns the phase of the feedback signal with the phase of the input signal. In this process, the phase locked loop shifts the phase of each of the clock signals relative to the phase of the input signal.

Abstract: A process for forming CMOS devices is disclosed in which disposable spacers are used to obtain a structure having improved gap-fill characteristics. First, gate film stacks are formed on the substrate. A shallow implant process is performed so as to form shallow source/drain implant regions. A layer of oxide and a layer of silicon nitride are deposited and etched to form a first set of spacers that extend on opposite sides of the gate film stacks. A second implant is performed so as to form intermediate source/drain implant regions. A set of disposable spacers are then formed that extend on opposite sides of each of the gate film stacks. A third implant process is performed so as to form deep source/drain implant regions. The disposable spacers are then removed, providing more space for the subsequently-formed contact to land.

Abstract: A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory cells, identifying faulty memory cells in the tested portion of the memory; writing an error map in another portion of the memory, the error map indicating the location of faulty memory cells found in the tested portion and, after executing the test routine and writing the error map, repairing at least some of the faulty memory cells using the error map. Once one portion of memory is tested, another portion is tested and a prior tested portion is used to write a new error map. Repairing, by analyzing the error map, is done at a slower speed than required for memory testing, allowing the use of a smaller logic section in the integrated circuit.