Abstract: A method of manufacturing semiconductor devices wherein defects on each layer of a semiconductor wafer are determined to be killer or non-killer defects by correlating critical area information on a die with defect size and classification information. The killer/non-killer defect information is tabulated in a defect table from which statistical yield predictions can be made.

Abstract: A flash memory device and a method to erase the flash memory device having a plurality of memory cells each having a source, a drain, a control gate, wherein the memory cells are organized in rows and columns with a wordline attached to the control gates of the memory cells in a row, with a bitline attached to the drains of cells in a column and a sourceline attached to the sources of cells in a row, and a switch connected between each sourceline and VS is controlled by sourceline decode circuit that opens a sourceline switch after the cells on the associated wordline verify as erased.

Abstract: A method to tighten the threshold voltage distribution curve in a memory device during a negative gate source erase by applying 5 volts to the sources of all the memory cells in the memory device, allowing the drains to float and applying a negative pulse followed by a positive pulse to all the control gates of all the memory cells in the memory device. During a negative gate channel erase, the drains and sources are allowed to float, the p-well is biased at plus 5 volts and a negative pulse followed by a positive pulse is applied to all the control gates of all the memory cells in the memory device.

Abstract: A method of manufacturing a semiconductor device that eliminates the N+ implant by replacement with resist spacers on n-channel gate structures and a standard Mdd implant. The N+ implant is thereby eliminated from the n-channel transistors and is replaced by an Mdd implant. The Mdd implant is simultaneously implanted into the core transistors and portions of the n-channel transistors unprotected by the resist spacers. The p-channel transistors are then implanted with a PLdd implant, the n-channel transistors are then planted with an NLdd implant, sidewall spacers are formed on all gate structures, the p-channel transistors are implanted with a P+ implant and the N+ and P+ contacts are then formed.

Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.

Abstract: Methods of manufacturing calibration wafers by forming a first layer of a material on a layer of a substrate material. In a first embodiment, calibration spheres are deposited on the first layer of material followed by an etch process that removes exposed portions of the first layer of a material. The calibration spheres are removed leaving pillars of the first layer of a material formed on the layer of a substrate material. The calibration spheres can be of various sizes forming pillars of various sizes. The calibration wafer with the various size pillars is scanned in a scan tool to determine the scan tool sensitivity. In a second embodiment, a layer of a second material is deposited on and around the various size pillars forming bumps over the various size pillars.

Abstract: A flash memory device and a method to read the flash memory device to decrease leakage current during read. The flash memory device has a source line control circuit connected to the sources of memory cells in a row and during read the source line control circuit connects the sources of the memory cells in a row to ground.

Abstract: A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive wires and combination conductive wires and vias are to be formed. A second layer of photoresist is patterned to expose portions of the semiconductor device under which combination conductive wires and vias are to be formed. A second layer of interlayer dielectric in which conductive wires are to be formed and a first layer of interlayer dielectric in which conductive vias are to be formed are simultaneously anisotropically etched to form cavities, which are simultaneously filled with a conductive material.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Abstract: A method of analyzing defects in a semiconductor manufacturing process by removing position offset of a selected scanning tool from the defect location information and adding position offset of a selected review analysis tool. The resulting defect location information from a scanner is based upon a true xy coordinate system and the analysis review tool reviews defect locations based upon its xy coordinate system.

Abstract: A method of manufacturing a flash memory device with blunted corners of the floating gate. The blunted corners of the floating gate allow a reduction in the required gate edge lifting that is designed into flash memory design and allows a shortening of the flash memory device to increase the density of flash memory devices that can be formed in a given area.

Abstract: A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and substrate terminal in the flash memory device, a positive voltage of between 4 to 5 volts is applied to the wordline to which the cell being read is attached and a voltage of less than equal to 2 volts is applied to the common source terminal.

Abstract: A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.

Abstract: A method of programming flash EEPROM devices that provides self-limiting multi-level programming states. Each cell in the flash EEPROM device can be programmed to have one of multiple threshold voltages. Each cell to be programmed has a programming voltage applied to the gate, a programming voltage applied to the drain and bias voltage applied to either the source (Vs) or to the substrate (Vsub) or both. The bias voltages Vs or Vsub are determined during a precharacterization procedure and each desired threshold voltage has a corresponding bias voltage Vs or Vsub that provides the desired threshold voltage during the programming procedure. The bias voltages Vs or Vsub are selected to provide self-limiting programming by the effective vertical field Ev=Vg −Vt−(either Vs or Vsub), where Vt increases during programming until the programming stops. The lateral field El=Vd−(either Vs and/or Vsub) is adjusted during programming to keep the lateral field El equal to Vd.

Abstract: A method of manufacturing a semiconductor device having metal structures formed on a first layer of interlayer dielectric, wherein the metal structures have a layer of TiN formed on the surface of the metal structures, a second layer of interlayer dielectric formed on and around the metal structures and layer of TiN, and a layer of photoresist formed on a surface of the second layer of interlayer dielectric. The method includes patterning and developing the layer of photoresist over selected metal structures exposing selected portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are etched down to a surface of the layer of TiN and the layer of TiN is then etched down to the surface of the metal structure.

Abstract: A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate glass serves as a self-aligned solid diffusion source to form LDD extensions. Spacers are formed on the walls of the opening in the phosphoro silicate glass and serve to reduce the length of the gate channel. A gate structure is formed by depositing a layer of gate oxide in the opening in the layer of phosphoro silicate glass and a layer of polysilicon is formed over the layer of gate oxide.

Abstract: A method of manufacturing semiconductor devices wherein defect images are isolated from reference images in an optical tool. Each layer of a semiconductor are inspected for defects and identified defect images are subtracted from reference images providing an operator of the optical tool a resultant image of the defects or a highlighted image of the defect.

Abstract: A method for erasing a flash EEPROM device that includes a plurality of memory cells. The plurality of memory cells is erase verified and an erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle repeats until all cells verify as erased and a flag is set to NO. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached and the flag is set to YES. This cycle repeats until all cells verify as not being overerased. If it is determined after the overerase verification step that the flag is set to YES, the plurality of memory cells is again erase verified and the procedure repeats. If it is determined after the overerase verification step that the flag is set to NO, the erase procedure is considered finished.

Abstract: A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is formed by implanting nitrogen and boron ions into the NMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the NMOS region at a selected concentration in the range of 1×1013 to 2×1015 ions per cm2 and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted in the NMOS region at a selected concentration in the range of 1×1012 to 1×1014 ions per cm2 and at a selected implantation energy in the range of 5-50 KeV. The shallow LDD regions in the PMOS region are formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and implantation energy levels.

Abstract: A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.