Abstract: Various embodiments of on chip-transformers constructed in separate metal layers in an insulator that serves as a dielectric which is formed on a substrate such as a silicon substrate. Windings with currents flowing in a first direction are constructed in a first metal layer and windings with currents flowing a second direction are constructed in a second metal layer. Windings in the first metal layer are connected to windings in the second metal layer by connectors such as vias. The transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary, a layout with the secondary separated the primary and rotated with respect to an axis of the primary, a layout in which the transformer is a two stage transformer and with the first stage constructed orthogonal to the second stage, or a transformer in which the windings are constructed in a toroidal layout.

Abstract: A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.

Abstract: A method of checking and repairing individual memory bits in a nonvolatile memory device having memory bits arranged in sectors. An unused sector is identified and each memory bit in the sector is checked to identify memory bits having a charge gain or a charge loss. An erase pulse is applied to each memory bit having a charge gain and a programming pulse is applied to each memory bit having a charge loss.

Abstract: A method of reviewing classification data and image data for defects detected in a series of semiconductor manufacturing processes. An inspection wafer is selected from a production lot of wafers and is inspected after the completion of each of the series of semiconductor manufacturing processes. The classification data for each defect is sent to a defect management system and an image for selected defects is sent to an image storage system. Identification data is sent to the defect management system and the image storage system. The image storage system sends a cookie to the defect management system allowing the defect management system to identify defects having an image. A operator controlled review station allows an operator to select defects for review that have an image available for review.

Abstract: A method of determining an accurate disposition decision for each inspected layer in a wafer lot wherein a measured defect density is compared to a calculated disposition criterion determined for each inspected layer. If the measured defect density is above the calculated disposition criterion the wafer lot is placed on hold and if the measured defect density is at or below the calculated disposition criterion the wafer lot is sent to the next process. The disposition criterion for each layer is determined from a yield value determined for each layer. The yield value is the yield necessary for each layer to obtain a profitable product and is determined from cost data for each die in the wafer lot and a risk factor determined by management and includes market data such as selling price and demand for the product. The yield value is combined with defect sensitivity determined for each layer. The defect sensitivity is determined from the combination of critical area and historical frequency for each layer.

Abstract: A method of nondestructively monitoring filled or unfilled via and trench profiles during the manufacture of semiconductor devices. A selected filled or unfilled via or trench is scanned with overlapped excitation pulses that form a temporally varying excitation radiation field causing a time-dependent ripple to be generated that is irradiated by a probe pulse that diffracts into at least two signal beams. One of the diffracted signal beams is detected and digitized to produce a digitized waveform signal that is analyzed in a CPU to obtain a frequency of the digitized waveform signal and is compared to characterization waveforms stored in a database to determine the profile of the selected filled or unfilled via or trench.

Abstract: A method to tighten the threshold voltage distribution curve in a memory device composed of multiple memory cells organized in rows and columns by soft programming each memory cell. Soft programming voltages that utilize the hot-carrier mechanism are selected and are applied sequentially to memory cells in wordlines. The soft programming voltages include a ramped voltage VGS of <3 volts, a VDS of <5 volts and a Vsub of <0 volts. The soft programming voltages are applied for a time period of <10 microseconds. The VT distribution is reduced to a maximum width of <2 volts. The soft programming is applied to the memory cells after the memory cells have been verified as having been erased and a having been overerase corrected.

Abstract: A method of manufacturing semiconductor devices wherein images of non-defect anomalies are captured and stored with image data and linkage data in a database. The non-defect anomaly data is stored in database for later retrieval.

Abstract: A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.

Abstract: A method of manufacturing a semiconductor wafer wherein each layer to be scanned is scanned in a scan tool after determination of whether the current recipe is contained in the scan tool. The recipe in the scan tool is compared to the current recipe stored in a server. If the recipe in the scan tool is not the current recipe the current recipe is loaded into the scan tool from the server. The recipes in the server are updated from associated scan tools.

Abstract: A semiconductor device having at least a first and second type of devices formed in the substrate of the semiconductor device and having a hydrogen free barrier layer formed by implanting nitrogen into a layer of amorphous silicon or polysilicon formed on the surface of the semiconductor device. A hydrogen getter layer is formed on the semiconductor device under the barrier layer. The hydrogen getter layer is removed from portions of the semiconductor device on which salicide layers are to be formed.

Abstract: A method of manufacturing a semiconductor wafer wherein a layer of hardmask material is formed on the surface of a metal layer formed on a layer of interlayer dielectric formed on a semiconductor substrate on and in which active devices have been formed. A layer of photoresist is formed on the surface of the layer of hardmask material, patterned and developed exposing portions of the underlying layer of hardmask material. The semiconductor wafer is placed in an etched and the layer of hardmask material is etched in a first process utilizing a combination fluorine and chlorine chemistry and the metal layer is etched in a second process utilizing a combination fluorine and chlorine chemistry.

Abstract: A method to reduce the peak electric field during erase of a memory device composed of multiple memory cells. The electric field E.sub.field of the memory cell during erase is determined by the equation E.sub.field .about.a.sub.g (V.sub.gate -V.sub.th +V.sub.tuv)+(a.sub.s -1)V.sub.source and varying gate voltages V.sub.gate are applied to the gate of the cell being erased so that the V.sub.gate -V.sub.th is constant during the erase procedure.

Abstract: A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.

Abstract: A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and source terminals in the flash memory device. A negative voltage (V.sub.D) is applied to all the substrate and all wordlines in the flash memory device. The negative voltage (-V.sub.D) is applied to the bitline to which the drain of the cell being read is attached and applying a positive voltage (V.sub.G) minus the voltage V.sub.D to the wordline to which the gate of the cell being read is attached.

Abstract: Memory devices having 1-transistor flash memory cells that in one embodiment allows bit-by-bit erase and in other embodiments allows erase of a multi-bit word. The word can be 8 bits, 16 bits, 32 bits, 64 bits or any size word. The memory devices have source bitlines that are connected to the bitline driver that controls the bitlines. The bitline driver and a wordline driver controls the voltages applied to selected bitlines, source bitlines while the wordline driver controls the voltage applied to selected wordlines to allow selected memory cells to be programmed, erased, or read.

Abstract: A method of manufacturing a semiconductor device with dual damascene structures. A first and second layer of interlayer dielectric separated by a first layer of etch stop material is formed on the surface of a semiconductor substrate on and in which active devices have been formed. A second layer of an etch stop material is formed on the surface of the second layer of interlayer dielectric. A layer of photoresist is formed on the second layer of etch stop material and is patterned and etched to expose portions of the second etch stop material. The exposed portions of the second etch stop material are anisotropically etched exposing portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are first anisotropically etched and then isotropically etched. The etch stop layer between the first and second interlayer dielectric is anisotropically etched and the first layer of interlayer dielectric is anisotropically etched.

Abstract: A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.

Abstract: An aluminum fill process for sub-0.25 .mu.m technology integrated circuits that has a reflow temperature less than 400.degree. C. that has low alloy resistivity and excellent electromigration characteristics. The aluminum allow is composed of Al-1% Ge-1% Cu.

Abstract: A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.