Abstract: Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.

Abstract: Systems, methods, and apparatus for preventing misuse of searches of a database system are provided. This prevention of misuse of database searches can enable reliable operation of the database system, as an improper query using a regular expression will not shut down or severely affect an application process that provides access to the database system. A thread of the application process determines whether an input character string matches the regular expression. To prevent misuse, a computational effort of the search is tracked, and compared to a threshold value. When the threshold is exceeded, an operation of the thread is exited or stopped.

Abstract: A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data recovery from corresponding sample sets. One function applied for the determination, includes taking a first mean transition position in a first group of sample sets, taking a second mean transition position in a second group of sample sets, computing a slope value for change in transition position, and making the determination based on the order of the plurality of samples, the first and second means, and the slope. The determined samples are obtained and data recovery is achieved. Sample sets can be modified according to equalization functions. Other modifications include encoding the sample sets for data compression.

Abstract: A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

Abstract: An improved regulator circuit, temperature compensation bias circuit, and amplifier circuit are disclosed.

Abstract: More efficient querying of a multi-tenant database using dynamic tuning of database indices. A layer of meta-data associates data items with tenants, e.g., via tags, and the meta-data is used to optimize searches by channeling processing resources during a query to only those pieces of data bearing the relevant tenant's unique tag.

Abstract: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.

Abstract: Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.

Abstract: Dual I/O data read is performed in an integrated circuit which includes a serial peripheral interface memory device. In one example, a second page read address is transmitted to the memory device using a first input pin and a second input pin concurrently, while transferring data from the memory device associated with a first page read address using a first output pin and a second output pin concurrently. The first page read address is associated with a first location in the memory device and the second page read address is associated with a second location in the memory device.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: A cooking apparatus includes a spatula assembly and a cooking container comprising an upper access opening and an inner, cooking surface having a spherical surface portion. The spatula assembly includes a spatula driver and a curved spatula pivotally mounted to the cooking container for moving along the cooking surface and about a pivot axis between first and second positions. The pivot axis passes through the center point of the spherical surface portion. The spatula assembly may be constructed so that at least one of the first and second positions is above the pivot axis. The curved spatula may also include a spatula body having an outer surface and a barrier member extending radially inwardly from the outer surface, the outer surface contacting the cooking surface of the cooking container.

Abstract: A cooking apparatus includes a spatula assembly and a cooking container comprising an upper access opening and an inner, cooking surface having a spherical surface portion. The spatula assembly includes a spatula driver and a curved spatula pivotally mounted to the cooking container for moving along the cooking surface and about a pivot axis between first and second positions. The pivot axis passes through the center point of the spherical surface portion. The spatula assembly may be constructed so that at least one of the first and second positions is above the pivot axis. The curved spatula may also include a spatula body having an outer surface and a barrier member extending radially inwardly from the outer surface, the outer surface contacting the cooking surface of the cooking container.

Abstract: A method of operating a laser to obtain an output pulse having a single wavelength, comprises inducing an intracavity loss into a laser resonator having an amount that prevents oscillation during a time that energy from the pump source is being stored in the gain medium. Gain is built up in the gain medium with energy from the pump source until formation of a single-frequency relaxation oscillation pulse in the resonator. Upon detection of the onset of the relaxation oscillation pulse, the intracavity loss is reduced, such as by Q-switching, so that the built-up gain stored in the gain medium is output from the resonator in the form of an output pulse at a single frequency. An electronically controllable output coupler is controlled to affect output pulse characteristics. The laser acts a master oscillator in a master oscillator power amplifier configuration. The laser is used for laser peening.

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.