Abstract: A CO2-facilitated transport membrane of excellent carbon dioxide permeability and CO2/H2 selectivity, which can be applied to a CO2 permeable membrane reactor, is stably provided. The CO2-facilitated transport membrane is formed such that a gel layer 1 obtained by adding cesium carbonate to a polyvinyl alcohol-polyacrylic acid copolymer gel membrane is supported by a hydrophilic porous membrane 2. More preferably, a gel layer supported by a hydrophilic porous membrane 2 is coated with hydrophilic porous membranes 3 and 4.

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract: A method for fabricating sputter targets is based on electrolytic deposition of metals or metal alloys onto the planar surface of a target backing plate. The target material can be electrolytically deposited onto the backing plate directly, or first electrolytically deposited onto the surface of a thin metal starting sheet which, after plating is complete, is then subsequently solder bonded to a substantially thicker metal backing plate. The disclosed technology includes steps for protecting regions of a target backing plate or starting sheet from deposition, said regions being other than the surface to be coated with target material by means of electrolytic deposition.

Abstract: One embodiment of the present invention provides a system for extending a gadget. During operation, the system initially executes a gadget extension which extends a host gadget. In doing so, the system obtains from the gadget extension a specifier for the host gadget and a specifier for an interface. Next, the system establishes a communication interface between the gadget extension and the host gadget through the interface. Finally, the system uses functionality of the host gadget within the gadget extension via communication through the communication interface.

Abstract: The present invention relates to dynamic optimization of system control over time. The need for dynamic optimization arises in many settings, as diverse as solar car power consumption during a multi-day race and retirement portfolio management. We disclose a reformulation of the control problem that overcomes the so-called “curse of dimensionality” and allows formulation of optimal control policies multiple period planning horizons. One optimal control policy is for power consumption by a solar car during a race, which involves many course segments, as course conditions vary through a day. Another is for risk in and consumption from a portfolio intended to support retirement. Both multi-period control policies take into account future uncertainty. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A guidance system for an agriculture platform that is capable of making decisions concerning the platforms direction and velocity regarding the pathway the platform is moving along as well as obstacles in the path of the platform, is provided. The autonomous agricultural platform guidance system and method will make it possible for small scale farming to take up automated mechanical farming practices which are currently only practical for large scale farming thus improving land utilization efficiency while lowering manpower costs dramatically.

Abstract: A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer material are selected. The buffer layer material is deposited on the substrate, the phase change material is deposited on the buffer layer, and the cladding layer material is deposited on the phase change material to form a memory cell element. The thickness of the phase change material is preferably less than 30 nm and more preferably less than 10 nm. The recrystallization time of the phase change material of the memory cell element is determined. If the recrystallization time is not less than a length of time X, these steps are repeated while changing at least one of the selected materials and material thicknesses.

Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

Abstract: A 3D phase change memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a threshold switching element. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.

Abstract: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.

Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: The present invention includes a method and device for updating a self-describing, structured document. A further aspect of the present invention is enabling client-based modification of the document. Additional aspects of the present invention are described in the claims, specification and drawings.

Abstract: A scalable video compression method and apparatus for encoding an input frame sequence having temporally sequential frames includes partitioning each of the frames of the input frame sequence into a top field and a bottom field to form a base layer sequence of fields and an enhancement layer sequence of fields. The base layer sequence and the enhancement layer sequence each comprise temporally alternating top and bottom fields of the partitioned frames of the input frame sequence. The base layer sequence and the enhancement layer sequence are encoded, wherein at least one field of the enhancement layer sequence is encoded in dependence upon at least one of the fields of the base layer sequence.

Abstract: Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements.

Abstract: A method and an apparatus for an ultrasound system provide compression of ultrasound signal samples after analog to digital conversion and before beamforming. The analog ultrasound signals received from an array of ultrasound transducer elements are digitally sampled by a plurality of analog to digital converters (ADCs) to produce a plurality of sequences of signal samples. Each sequence of signal samples is compressed to form a corresponding sequence of compressed samples. The resulting sequences of compressed samples are transferred via a digital interface to an ultrasound signal processor. At the ultrasound signal processor, the received sequences of compressed samples are decompressed. The typical processing operations, such as beamforming, downconversion and detection, are applied to decompressed samples. This abstract does not limit the scope of the invention as described in the claims.

Abstract: Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.

Abstract: The invention addresses the lack of comprehensive and quantitative methods for measurements of unwanted visual “mura” effects in displays and image sensors. Mura is generated by errors that are significantly smaller than what is needed for the function of the device, and sometimes smaller than the random variations in the patterns or structures. Capturing essentially all mura defects in a workpiece in a short time requires a daunting combination of sensitivity, statistical data reduction and speed. The invention devices an inspection method, e.g. optical, which maximizes the sensitivity to mura effects and suppresses artifacts from the mura inspection hardware itself and from noise. It does so by scanning the sensor, e.g. a high-resolution camera, creating a region of high internal accuracy across the mura effects. One important example is for mura related to placement errors, where a stage with better than 10 nanometer precision within a 100 mm range is created.