Abstract: Apparatus for condensing hydrocarbons, such as but not limited to butane and propane, from a stream of natural gas includes as its primary components a pre-cooler assembly, a chiller assembly, a refrigerant compressor/condenser assembly, and separator assembly. In the pre-cooler assembly warm gas entering the apparatus is cooled by counter-current flow heat exchange with cooled natural gas exiting the apparatus. The chiller assembly of the apparatus the hydrocarbon stream is cooled in co-current flow heat exchange with a first refrigerant tube, carrying a first refrigerant which is itself cooled in co-current heat exchange with a second refrigerant tube disposed in coaxial relationship with the first refrigerant tube. Both first and second refrigerant tubes are disposed in coaxial relationship with an outer jacket conveying the gas stream through the chiller assembly. Condensed hydrocarbons are separated from the gas stream in the separator assembly.

Abstract: A method and system for characterization of fault conditions within a subterranean volume. In one embodiment, the system comprises means for mathematically modeling stress conditions, to predict breakout conditions along a borehole trajectory. The system further comprises means for sensing actual breakout conditions along the borehole . Predictive breakout data is compared with sensed breakout conditions to assess correlation between predictive data and actual data, verifying the accuracy of the stress model. The mathematical model may be revised to reflect the presence of an active fault plane in the volume, the presumed fault plane not being intersected by the borehole. The revised model is used to generate new predictive data. Revising the stress model and assessing correlation between predictive and actual breakout conditions is repeatable to achieve an optimally accurate stress model reflecting fault conditions proximal to but not necessarily penetrated by the borehole.

Abstract: This invention relates generally to a method for growing single-wall carbon nanotube (SWNT) from seed molecules. The supported or unsupported SWNT seed materials can be combined with a suitable growth catalyst by opening SWNT molecule ends and depositing a metal atom cluster. In one embodiment, a suspension of seed particles containing attached catalysts is injected into an evaporation zone to provide an entrained reactive nanoparticle. A carbonaceous feedstock gas is then introduced into the nanoparticle stream under conditions to grow single-wall carbon nanotubes. Recovery of the product produced can be done by filtration, centrifugation and the like.

Abstract: A pumped voltage generating circuit for a semiconductor device is disclosed in which measures are taken to minimize undesirable gate-induced diode leakage, especially during standby or idle states of operation of the device. In one embodiment, the pumped voltage generating circuit comprises a charge pump for generating a voltage which is either higher than the voltage of an externally-applied positive supply voltage or lower than the voltage of an externally-applied negative supply voltage. In one disclosed embodiment, a voltage pump generates a pumped voltage and a voltage regulator provides a regulated voltage, where the pumped voltage is characterized as being either more positive than the most positive externally-applied positive voltage supply signal or more negative than the most negative externally-applied negative voltage signal. The pumped voltage and the regulated voltage are applied to respective inputs of a multiplexer receiving a select signal.

Abstract: A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal “stripes” therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction.

Abstract: A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to the piezoelectric transducer induces a unidirectional vibration of the transducer. The vibration is propagated through the beams and reflected by the reflecting boards in a closed polygonal loop. The final reflection direction is perpendicular to the original vibration. A circular or elliptical vibration of the apparatus results. The circular or elliptical vibrational energy can be imparted to the wire bond of an integrated circuit to add strength to the connection.

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency.

Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

Abstract: A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polyimide, partially-cured polyimide, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention.

Abstract: A system and method of the type for quickly mobilizing a unit for dredging a layer of material from a water bottom is provided. The dredging system includes: a motorized, substantially self-contained vessel positioned above a borrow site, at least one dredging shoe extended from the vessel to a bottom of a water adapted for dredging a material from the bottom to a pre-selected depth, a power source positioned on the vessel in operational connection with the dredging shoe for drawing the material into the shoe and transporting the material through a conduit to a deposit site, and a dredging motivation system connected to the vessel for moving the vessel and the dredging shoe along a dredging path.

Abstract: An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.

Abstract: A method and apparatus for performing a block-write to a memory device comprising at least one register, a data input port, at least one memory bank, and a hardware device to block-write data from the register to the memory device, including receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from a write logic unit to the memory bank at a double data rate as determined by the clock cycle.

Abstract: A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: The present invention provides a ball grid array (“BGA”) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.

Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protect on and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A Storage Manager that dynamically manipulates and partitions the secondary storage of a computer device without re-writing or revising the secondary storage after each manipulation. The Storage Manager is represented by executable code between the firmware level and the run time operating system and application program level of a computer device. Means are provided to transfer control of the computer device to the Storage Manager prior to the run time operating system or application program gaining control of the computer device. Storage Manager includes a Virtual Table of Contents (VTOC), in which relevant identifying information is contained for each Partition of the secondary storage. At least one Cabinet is created, containing a list of Partitions. Each Cabinet can have a separate list of Partitions, and one Partition can be included in more than one Cabinet. One of the Cabinets is designated as an Active Cabinet. Upon continuation of the boot sequence, the contents (ie.

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a heat-dissipating lead-frame, a semiconductor chip coupled to the heat-dissipating lead-frame, and an insulating package encapsulating the semiconductor chip and an internal portion of the heat-dissipating lead-frame. The heat-dissipating lead-frame is constructed of a single material. A process is provided for fabricating a semiconductor device assembly. The process includes providing a lead-frame that includes a paddle with external and internal portions, providing a semiconductor chip, thermally coupling the semiconductor chip to the internal portion. The process also includes encapsulating the semiconductor chip and the internal portion in an insulating material.