Abstract: The present invention provides a ball grid array (“BGA”) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.

Abstract: A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to the piezoelectric transducer induces a unidirectional vibration of the transducer. The vibration is propagated through the beams and reflected by the reflecting boards in a closed polygonal loop. The final reflection direction is perpendicular to the original vibration. A circular or elliptical vibration of the apparatus results. The circular or elliptical vibrational energy can be imparted to the wire bond of an integrated circuit to add strength to the connection.

Abstract: A method and apparatus for programmable field emission display comprising an array of cathodoluminescent elements. Each cathodoluminescent element in the array is responsive to separate select signals to cause light to be emitted from said display at a location in the array corresponding to each separate cathodoluminescent element. In one embodiment, to account for processing variation and the like, each cathodoluminescent element is provided with a programmable element for adjusting the operating level of the associated cathodoluminescent element in response to select signals of predetermined voltage levels. Each programmable element includes a charge storage device and is initially programmed by storing a level of electric charge thereon such that uniformity of operation among the plurality of cathodoluminescent elements in the array is improved. In one embodiment the programmable element comprises a floating gate transistor.

Abstract: The present invention provides a semiconductor device assembly comprising a semiconductor chip, a heat sink having internal and external portions, and a housing that encapsulates the semiconductor chip and the internal portion. The internal portion thermally couples to one surface of the semiconductor chip. The present invention also provides a process of fabricating a semiconductor device assembly. The process includes: providing a semiconductor chip; providing a heat sink having internal and external portions; mechanically attaching a face of the chip to the internal portion; and applying an encapsulating material around the semiconductor chip and the internal portions.

Abstract: A method and apparatus for limited reprogrammability of fuse options in a semiconductor device is disclosed. In one embodiment, option circuitry includes a plurality of programmable devices each actuable from a first state to a second state and an option circuitry, which is coupled to the plurality of programmable devices to receive a plurality of logic signals reflecting the respective states of the plurality of programmable devices. The option circuitry is responsive to the plurality of logic signals to assert a particular one of a plurality of distinct option signals. The particular option signal is determined based on the particular combination of respective states of the plurality of programmable devices. The semiconductor device is responsive to assertion of each of the plurality of distinct option signals to operate in a distinct one of at least two operational modes.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A method and apparatus for generating a timing signal for a semiconductor device, wherein the timing of rising and falling edges in the timing signal can be very precisely controlled. In one embodiment, a serial data stream derived from data stored in a memory device is applied to the inputs of first and second programmable delay elements each adapted to introduce a delay into the serial data stream. The resulting first delayed serial data stream is applied to the SET input of a flip-flop circuit; the resulting second delayed serial data stream is applied to the RESET input of the flip-flop. The output of the flip-flop constitutes the generated timing signal. The rising and falling edges of the timing signal are controlled through manipulation of the lengths of the delays introduced by the first and second delay elements into the serial data stream. Manipulation of the delay times is accomplished through adjustment of analog programming voltages applied to the respective delay elements.

Abstract: A method and apparatus for using photoemission to determine the endpoint of a dry etch process. In one embodiment, the endpoint of a dry etch process is determined when the dry etch process is acting on a substrate comprising a layer of a first material overlying a second material. The substrate is illuminated with a beam of monochromatic light. The photon energy of the monochromatic light is greater than the work function of one of the two materials, and less than the work function of the other material. Thus the beam of light is capable of inducing photoemission of electrons in only one of the two materials: the material with a work function less than the photon energy of the beam of light. The electrons emitted by the photoemitting material are collected. The current generated by the collected stream of electrons, the photocurrent, is amplified. A time-series of amplified photocurrent measurements is monitored for changes that correspond to the endpoint of the dry etch process.

Abstract: A method and apparatus for testing of semiconductor memory devices. In one embodiment, a test mode of operation is defined for a memory device. In a normal mode of operation, a row line than addressed memory cell is asserted in response to applied external signals corresponding to the beginning of a write-back phase of a read-modify-write cycle. The row line is deasserted on response to applied external signals corresponding to the end of the write-back phase. In the test mode of operation, the row line is asserted in response to the appropriate applied external signals, but deassertion in response to the appropriate applied external signals is suppressed. Instead, deassertion of the row line is forced only upon expiration of a programmable, predetermined time interval following initiation of the write-back phase. The programmable delay can be established by means of an R-C time constant delay circuit.

Abstract: In one aspect, the invention relates to automatically providing enhancements to computer security software whenever the enhancement becomes available. In another aspect, the invention relates to an integrated system for assessing security vulnerabilities of a computer and/or a computer network.

Abstract: The present invention provides a ball grid array (“BGA” ) assembly and process of manufacturing for reducing warpage caused by the encapsulation of the associated semiconductor chip. The assembly and process includes coupling a substrate between a semiconductor chip and a BGA structure; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the semiconductor chip.

Abstract: An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.

Abstract: An in its various embodiments is a method and apparatus for electrostatic discharge protection. In one aspect of the present invention, an integrated circuit device capable of providing electrostatic discharge protection for use on a printed circuit board containing a possible source of electrostatic discharge and operational circuitry is provided. The integrated circuit device includes an input coupled to the possible source of electrostatic discharge, an output coupled to the operational circuitry on the printed circuit board, a capacitance structure between the input and the output, and a switch in series with the capacitance structure. The integrated circuit also provides, a method for protecting a printed circuit board from electrostatic discharge by switching the discharge to a capacitance structure for subsequent dissipation into the printed circuit board.

Abstract: A method and apparatus for limited reprogrammability of fuse options in a semiconductor device is disclosed. In one embodiment, option circuitry includes a plurality of programmable devices each actuable from a first state to a second state and an option circuitry, which is coupled to the plurality of programmable devices to receive a plurality of logic signals reflecting the respective states of the plurality of programmable devices. The option circuitry is responsive to the plurality of logic signals to assert a particular one of a plurality of distinct option signals. The particular option signal is determined based on the particular combination of respective states of the plurality of programmable devices. The semiconductor device is responsive to assertion of each of the plurality of distinct option signals to operate in a distinct one of at least two operational modes.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: An improved system and method of automating the identification, remediation and verification of computer program code fragments which have no specific search criteria using an iterative dynamic self propagating global symbol table. Computer code is input and then decomposed into predefined table entries. This is used to verify that all of the source code is present and to provide forward and backward linking to related code fragments containing various levels of dynamically modified confidence factors. Global computer program changes can then be made regardless of the initial state of the code fragment or number of redefinition's in a swap-by-propagation fashion. Remediations are logged to provide verification data and to insure complete testing.

Abstract: A socket device for receiving a connection pin is disclosed, the socket device including a substrate having an upper surface. The socket device includes a connection pad disposed on the upper surface and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad.

Abstract: A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to the piezoelectric transducer induces a unidirectional vibration of the transducer. The vibration is propagated through the beams and reflected by the reflecting boards in a closed polygonal loop. The final reflection direction is perpendicular to the original vibration. A circular or elliptical vibration of the apparatus results. The circular or elliptical vibrational energy can be imparted to the wire bond of an integrated circuit to add strength to the connection.

Abstract: The invention discloses the process of modulating data streams to create discrete channels of information in network environments. After data channelization, networks, workgroups, workstations or other end-user devices are provided or denied access to specific data streams or channels. Devices normally involved in network interfaces or network distribution backbones are configured to provide only channels of data that have been authorized. The network status controller retains and stores status changes related to network access in general, and specifically to discrete channel access.

Abstract: The present invention provides a semiconductor device assembly comprising a semiconductor chip, a heat sink having internal and external portions, and a housing that encapsulates the semiconductor chip and the internal portion. The internal portion thermally couples to one surface of the semiconductor chip. The present invention also provides a process of fabricating a semiconductor device assembly. The process includes: providing a semiconductor chip; providing a heat sink having internal and external portions; mechanically attaching a face of the chip to the internal portion; and applying an encapsulating material around the semiconductor chip and the internal portions.