Abstract: A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern.

Abstract: Methods and apparatus determining codevectors in response to a speech signal include a first codebook member which stochastically determines the characteristics of a bi-pulse codevector representative of a target vector associated with the speech signal and for removing the bi-pulse codevector from the target vector thereby forming an intermediate target vector. A second codebook member stochastically determines the characteristics of a second bi-pulse codevector in response to the intermediate target vector. In one embodiment of the invention a third codebook member adaptively determines a first codeword in response to the target signal and forms another intermediate target signal and a fourth codebook member stochastically determines a second codeword in response to the intermediate target signal.

Abstract: An analog resistive touch screen is powered by a current source responsive to a stored digital control value. The current source is calibrated by comparing the excitation voltage across the touch screen to a desired voltage to produce a comparison signal, and adjusting the digital control value in response to the comparison signal so that the excitation voltage becomes substantially equal to the desired voltage. The power supply can therefore be easily constructed in a low-voltage CMOS integrated circuit having a minimal power consumption without sacrificing touch screen resolution. Preferably the comparison of the excitation voltage to the reference voltage is performed by an analog-to-digital converter that is later used in a normal conversion mode for digitizing the touch screen coordinates.

Abstract: The invention provides a method and system for extending channel access in a wireless communications system employing half duplex subscriber units. The subscriber units transmit multi-block bursts to improve the burst throughput over half duplex subscriber units that transmit only single-block bursts. The number of blocks per burst is selected based on the code rate used and may be selected in a manner that also maximizes the system throughput. The subscriber unit includes a block processor for assembling the blocks of data with overhead based on the code rate, a burst formatter for combining the blocks and formatting the combination based on the code rate, and a process manager for selecting the number of blocks to be transmitted in each transmit burst.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a tone signal generator. The tone signal generator includes first tone signal generation means for producing a dual-tone, multi-frequency ("DTMF") audio signal; second tone signal means for producing a plurality of non-DTMF audio signals; storage means for storing data that represents at least one channel of an output audio tone signal; and selection means for selectively loading the DTMF signal into the storage means and for selectively accumulating the non-DTMF signals into the storage means so as to generate the output tone signal.

Abstract: A method for changing the frequency of a low-pass Finite Impulse Response (FIR) filter with a fixed frequency clock utilizes a decimation-by-coefficient technique. The decimation-by-coefficient method utilizes a single set of coefficients that are stored in a coefficient Read Only Memory (ROM) (64). Data is input to an elastic buffer (60) with multiplications performed by a multiplication circuit (62). To realize a low frequency filter, all coefficients are utilized in the multiplication operations with sequential multiplies. These are accumulated in register (70), this providing a high precision filter. To increase frequency by a factor of two--to decimate the coefficients by a factor of two, it is only necessary to utilize every other coefficient, such that only a single fixed clock (78) is required.

Abstract: Competition between subscriber stations attempting to access reverse channels in response to Temporary Equipment Identifier (TEI) messages is limited by requiring the subscriber stations to wait for a predetermined amount of time. The time delay is selected on the basis of a random number and a factor based upon the number of TEI messages broadcast. The method for determining response opportunities for subscriber stations also includes a back-off phase at the first stage. The time delays to the defer phase is based upon a random period of time and a predetermined maximum based upon the time needed for the microslots containing a TEI message.

Abstract: A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: Motion video may be imported into a personal or portable computer through an I/O port having a limited data bandwidth, such as a PCMCIA interface. Motion video data is compressed by sub-sampling both luminance and chrominance difference data for different sized groups of pixels. The compression apparatus may be formed on a PCMCIA card which interfaces with a personal or portable computer. Motion video data, compressed by as much as 5:1 or 6:1, is transferred through the PCMCIA card to a host computer. The host computer may serialize the compressed data and store the data in serialized compressed format in a video memory of a video controller. The video controller is provided with decompression circuitry to decompress the motion video data into luminance and chrominance difference data. The luminance and chrominance difference data is converted into RGB data and displayed in a video display.

Abstract: Interrupts are prioritized such that selected interrupts use shadow registers to save the current state of the machine, whereas other interrupts use a software implemented interrupt service routine (ISR) to save and restore the current machine state. Hence, the number of nested interrupts that can be serviced will not be limited to the depth of register shadowing.

Abstract: An amplifier having an inverting and a non-inverting input and at least one output is compensated by dynamically varying the transconductance of a gain stage in accordance with the gain of the output stage of the amplifier. The amplifier comprises a gain section having at least one output, where a gm of the gain section varies with a transconductance control signal. The amplifier further comprises an output stage comprising a output drive device controlled by an output of the gain section. A bias control circuit is coupled to drive the transconductance control input of the gain section, the bias control circuit increasing a differential mode transconductance of the first gain stage when the active pullup or pulldown output drive device has low gain.

Abstract: A VCO includes a ring oscillator formed by connecting a plurality of voltage controlled inverting delay cells together, a biasing circuit for providing a bias voltage to each of the voltage controlled inverting delay cells, and a source-follower transistor for providing a control voltage to the biasing circuit and voltage controlled inverting delay cells. Each of the voltage controlled inverting delay cells includes a first and a second plurality of transistors which define two outputs of the voltage controlled inverting delay cell, and a clipper transistor connected between the two outputs to short them together whenever a difference between a bias voltage provided to a gate of the clipper transistor by the biasing circuit and a voltage on either one of the two outputs exceeds a threshold voltage of the clipper transistor.

Abstract: A device for use in a computer system, particularly a personal computer (PC) which provides compatibility for a proposed ISA plug and play (PNP) standard. The device of the present invention is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.

Abstract: A computer system including one or more PCMCIA expansion slots allows video and/or audio capabilities to be added to the system through a standard PCMCIA interface, utilizing multimedia type PCMCIA peripheral cards. A PCMCIA host adapter integrated circuit interrogates a PCMCIA peripheral card to determine whether or not the PCMCIA peripheral card is a multimedia type PCMCIA peripheral including video or audio capability. If the PCMCIA peripheral card is a multimedia type peripheral, the PCMCIA host adapter integrated circuit couples the PCMCIA peripheral card directly to the graphics and sound controller integrated circuits, using the standard PCMCIA interface and bypassing the host system bus. Otherwise, if the PCMCIA peripheral card is a standard PCMCIA peripheral, then the PCMCIA host adapter integrated circuit interfaces communications between the PCMCIA peripheral card and the host system bus in a conventional manner.

Abstract: A method and apparatus for arbitration among users for a resource has a single shared user request line over which each of the users asserts request signals for use of the resource. Dynamic priority assignment is provided, in which the sequence of users is changed as a function of the last user to use the resource. A time multiplexed format for arbitration is followed, with each user keeping track of which user's turn it is to request use of the resource. This prevents starvation of an individual user and allows great flexibility in assigning priority to the users, while reducing pin counts and signal traces.

Abstract: The kiln with displaceable frames, designed to contain also manufactured articles of considerable mass avoiding any direct contact between them and the motor rollers which causes thickenings, is provided with a formation of short transverse, non-through, rollers (22), distributed in two opposite rows to define at least one plate of transport, said rollers extending in an overhanging manner towards the inside of the lateral walls of the kiln; a loading frame (28), rectangular or square, constituted by a pair of stringers (29) connected rotationally to the internal ends of said rollers and interconnected by transverse elements (30) for supporting the manufactured articles to be treated, is introduced into the kiln and guided by lateral surfaces; the kiln is used in industries in which drying or firing of manufactured articles, for instance ceramic articles such as sanitary apparatus, is made.

Abstract: A measurement device or system (11) for determining features of a three-dimensional object (20) from two-dimensional images includes a projector (27) for projecting a pattern (73) upon the object (20), at least one imager (17, 19) for obtaining multiple sets of image data of the illuminated object (20) and a processor (47) for obtaining a three-dimensional image (81) of the object (20) from the multiple sets of data.