Abstract: A method of delivering data in an on-time manner across a communicating environment, such as multimedia data in a network or broadcast environment. The data is transmitted from a data pump at a revised transmission time which is a function of a base transmission time and a delay value. The delay value is calibrated by monitoring one or more processes between the data pump and an associated controller which receives requests from clients. The controller may include an application server which handles the requests, and a control server which processes commands from the application server and provides corresponding control functions to the data pump.

Abstract: A method of accessing a cache used by a processor of a computer system, to eliminate arbitration logic which would otherwise be required to handle operations from multiple snooping devices. A plurality of cache directories are provided in the cache, respectively connected directly to a plurality of snooping devices using a plurality of interconnects. An operation from a given snooping device is then handled by using a respective cache directory to issue a response to a respective interconnect. For example, a first cache directory may be connected to a first interconnect on a processor side of the cache, and a second cache directory may be connected to a second interconnect on a system bus side of the cache. This construction allows handling of operations from multiple snooping devices without having to use critical path arbitration logic. Furthermore, this construction allows for improved cache access due to the physical placement of the multiple cache directories.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address of a memory device of the computer system, and each cache snoops the interconnect to detect the message.

Abstract: A CMOS differential amplifier uses a first pair of complementary MOSFETs and a second pair of complementary MOSFETs coupled to a power supply (by another pair of MOSFETs) in such a manner as to be self-biasing and have improved channel-length modulation characteristics. An N-type MOSFET couples the first and second complementary MOSFET pairs to ground potential via a first resistor, and a P-type MOSFET couples the first and second complementary MOSFET pairs to a power-supply via a second resistor. The first and second resistors can be provided using non-salicided N-type MOSFET resistors. The third N-type MOSFET preferably has a low-threshold voltage, including a zero-threshold voltage, and the substrates of the P-type MOSFETs in the first and second complementary pairs are further preferably connected to the sources of those MOSFETs in order to reduce body-sensitivity effects.

Abstract: A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results generated by the floating-point processor, but normalization can sometimes result in an underflow condition, which requires denormalizing the intermediate result. The present invention provides a method of determining an amount to shift the mantissa of the intermediate result to obtain a final result while avoiding ever producing an exponent that is out of range. The invention also allows denormalized numbers to be stored in the floating-point registers in a denormalized form. The method of determining the shift amount first requires a determination of whether both, or only one, of the product and adder operands are denormalized. If both are denormalized, then the shift amount is equal to the addend alignment amount.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit.

Abstract: A method of automatically adjusting the line speed for communication between a client having data communications equipment (DCE) and a server having data terminal equipment (DTE). A first connection is established between the client and the server at a first speed, and the client sends a first synchronous data link control (SDLC) frame that identifies a requested speed. The server than sends a second SDLC frame in response to the first SDLC frame, identifying a second speed, wherein the second speed is the smaller of the requested speed and a predetermined (maximum) speed. If the client determines to communicate at the second speed, it drops the first connection, establishes a second connection at the second speed, and sends a third SDLC frame at the second speed; the server then sends a fourth SDLC frame in response to the third SDLC frame at the second speed, to confirm the connection, and data transmission follows.

Abstract: A low power communications bus uses a current source at one end of a transmission line, and a driver at the other end of the transmission line which generates a logic state based on the sensed current level. The invention is particularly suited for interconnecting a computer processor and its on-board caches. The driver at the load end of the transmission line includes an induction coil, and a magnetoresistive element located adjacent the coil. Separate ground planes can be provided for the coil and the magnetoresistive element, to avoid ground loops.

Abstract: A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each cache snoops an interconnect to detect the message, and transmits a response to the message, wherein a shared intervention response is transmitted to indicate that a cache containing an unmodified value corresponding to the address of the memory device can source the value. A priority is associated with each response, and system logic detects each response and its associated priority, and forwards a response with a highest priority to the requesting processing unit. The protocol may include prior-art coherency responses such as an invalid response, a modified intervention response, a shared response, and a retry response. Either the retry response or the shared intervention response may be assigned a highest priority.

Abstract: A method of providing a dynamic abstraction layer, such as a boot filesystem, for a computer having a particular hardware platform, in order to make a basic operating system more portable. The method includes storing the dynamic boot filesystem in a protected space in the computer before the normal boot sequence, and then retrieving the dynamic boot filesystem from the protected space during the boot sequence and loading the retrieved dynamic boot filesystem. The computer firmware first loads a simulated boot image which contains the dynamic boot filesystem, and then loads an operating system boot image which contains the operating system and instructions for retrieving the dynamic boot filesystem. A default boot filesystem may be used if no previously stored dynamic boot filesystem is found. In a UNIX embodiment, the dynamic boot filesystem includes a hardware-dependent PAL (Portable Assist Layer).

Abstract: A method and system are provided which allow heterogeneous computing systems to have direct access to the same data storage areas on a shared data storage subsystem such that the method and system are transparent to the heterogeneous computing systems. The method and system achieve the foregoing via the following steps. A data storage subsystem controller queries all computing systems having direct access to the same data storage areas of a shared data storage subsystem as to the operating systems utilized by such computing systems. In response to answers received in response to the queries, the data storage subsystem controller creates and stores meta-data which associates each computing system having direct access with whatever operating system is running on each computing system having direct access.

Abstract: An improved method of providing an operating system for a computer by defining an interface between the operating system and the computer's firmware. An executable file (soft ROS) is placed in a boot image so as to run, before execution of the real operating system, in response to the firmware seeking the operating system. The soft ROS includes instructions to determine whether the firmware conforms to the standardized interface. If so, then no special action is taken and control is passed to the operating system, but if the firmware is non-conforming in any manner, the soft ROS executes a firmware emulation module which provides the interface with the operating system. The firmware emulation module can provide missing dependencies of the firmware to the operating system, fix a defect in the firmware, or translate functions of the firmware to the pre-defined interface. This method isolates the operating system from firmware dependencies, making the operating system more portable.

Abstract: A dynamic logic circuit operates in a normal mode, and in a safe mode for which the circuit is less susceptible to noise than with the normal mode. The dynamic logic circuit includes a logic network having at least one input, a precharge device having a storage node connected to the logic network, and a device for varying a capacitance of the storage node to provide the normal and safe modes of operation. In one embodiment, the capacitance at the storage node is varied by selectively connecting the storage node to a capacitor, particularly to a DRAM cell capacitor. The DRAM cell is advantageously fabricated on a chip in close proximity to the storage node. A logic process using a plurality of such dynamic logic circuits can have means for independently operating each of the circuits in the safe mode, and the circuits can be monitored during the normal and safe operation modes to determine whether any are failing during the normal operation mode, e.g., due to excess noise.

Abstract: A computer file system, particularly adapted to UNIX operating systems, for transparently allowing access to and modification of snapshot objects, i.e., files, directories, and symbolic links. The file system creates a mountpoint directory and dynamically searches the computer system to find a requested file object, manifesting a representation of the requested file object in the mountpoint directory if it is found. If an earlier representation of the requested file object already exists (in the mountpoint directory), then any further requests for the file object are directed to the earlier representation. Searching can be performed along a viewpath having two or more independent search paths, including those based on an object name, or based on an object name extension. The binding file translation is done entirely within the kernel to speed up processing, as well as minimize the overhead required to establish mountpoints across different machines.

Abstract: A method and system for allowing one or more attached devices to access a computer bus. The objects of the method and system are achieved as is now described. At some particular instant in time, prioritized queues are loaded with one or more requests for access from one or more devices whose assigned priority levels correspond to the priority of the queue into which the requests for access are loaded. Requests for access, which are resident within a current queue, are preferentially granted in a sequential fashion until the current queue is emptied, after which at least one request for access from a lower in priority queue relative to the current queue is granted before responding to other requests for access, such that at least one request for access is periodically granted from a lower in priority queue relative to the current queue.

Abstract: A method of saving the context of a plurality of registers in a computer processor, requires determining whether the processor registers have a first size or a second size, and saving the contents of the registers in a buffer using a first set of instructions if the processor registers have the first size (e.g., 64 bits), and using a second set of instructions if the processor registers have the second size (e.g., 32 bits). If the processor registers having the first size, the method may further include the steps of determining whether the processor is operating in a first mode (e.g., 64-bit mode) or a second mode (e.g., 32-bit mode), and then saving the contents of the registers in the buffer using the first set of instructions if the processor is operating in the first mode, but using the second set of instructions if the processor is operating in the second mode.

Abstract: An actuator structure includes a flexure suspension with a flag appendage having a cantilevered portion extending parallel to the arm-suspension to form a gap therebetween. The flex cable that connects to the device electronics has an elongated portion secured to the side of the arm-suspension assembly presenting termination pads, which extend to the cable edge, along the elongated portion side and in alignment with the gap between arm-suspension and flag. The leads extending from the transducer are fanned out and extend across the gap. The leads are bonded to the arm-suspension and to the lead cantilevered portion immediately adjoining the gap. To terminate the leads, the flag is folded down 90 degrees, bringing the leads into contact with the termination pads where they are ultrasonically bonded. The flag is then bent toward its original position causing the fine lead wires to separate between the flag cantilever portion bond and the ultrasonically bonded termination.

Abstract: A computer system is provided with microprocessor clocking control by providing a clock having output timing signals which vary based on input signals to the clock, setting timing parameters for the clock using a service processor which sends the input signals to the clock, and controlling the primary processor using the output timing signals from the clock. The service processor can be used to modify a pulse width of at least one of the output timing signals, and to delaying a first one of the output timing signals with respect to a second one of the output timing signals. Separate clock signals can be provided for the primary processor and other system components, such as a cache connected to the primary processor, a memory device of the computer system, or an input/output device of the computer system. The clock has a programmable duty-cycle control circuit. The duty-cycle control circuit may use delay chains having a plurality of individually selectable delay elements.

Abstract: A name space registry manages name space data within a computer operating system including configuration and initialization data. The registry provides access to the configuration information by means of an application program interface (API) for programs which can operate with the name space registry. Backward source-code compatibility is provided for older applications by maintaining configuration and initialization files that the older applications use to store configuration and initialization data under their traditional file names and with the traditional contents. Thus the older applications can directly access these files. The registry provides newer programs access to these configuration and initialization files through API program calls.

Abstract: A device for measuring the density of a formation uses a high-energy pulsed neutron source which induces gamma rays in the formation, and determines a gamma diffusion length of the formation based on the attenuation of gamma rays produced by inelastic scattering of fast neutrons. The borehole tool houses the neutron source along with a near gamma ray detector and a far gamma ray detector. The gamma ray detectors are located at different distances from the fast neutron source and spaced sufficiently from the fast neutron source such that dependence of inelastic gamma counts on fast neutron transport and gamma production of the formation is substantially reduced. Gamma ray events can be sorted and counted in time- and energy-dependent bins. The present invention has several advantages over gamma-gamma logging, including deeper penetration of gamma, and is also superior over systems which measure, e.g., hydrogen-based porosity.