Abstract: A sock whose leg portion has wicking regions interspersed among fabric folds which are adapted to increase the effective surface area of the leg portion. The foot and leg portions of the sock may be constructed of the same material, such as synthetic, hydrophobic yarns, and formed in a unitary manner, either by weaving or knitting. The wicking regions may be formed using stitching along outer edges of a plurality of diamond shapes. Alternatively, the wicking regions may be formed by a set of first fabric bands, wherein the fabric folds comprise a set of second fabric bands, and the first and second bands alternate horizontally along a length of the tubular leg portion. The first fabric bands are preferably elastic or stretchable to maintain the first fabric bands in intimate contact with a wearer's skin.

Abstract: A method of determining a holdup value for a multiphase fluid. A first holdup component is calculated using a first detection technique which is insensitive to small inclusions of a first fluid constituent (hydrocarbons) dispersed in a second fluid constituent (water). A second holdup component is also calculated using a second detection technique which determines a percentage of the small inclusions of the first fluid constituent that are dispersed in the second fluid constituent. The first and second holdup components are then combined to yield a total holdup value. The method can further compensate for displacement of the second fluid constituent by the small inclusions of the first fluid constituent. The second holdup component is preferably calculated by inferring a maximum heavy phase density (MHPD) of the multiphase fluid.

Abstract: A circuit for conditionally restoring an execution unit in a computer processor, to reduce power consumption. Execution units, such as an arithmetic logic unit, shift/rotate unit, multiply unit, etc., have bits in transit that flow through a series of logic gates. These gates must be precharged after an operation has occurred to prepare the unit for the next operation. The conditional restore circuit evaluates either the data input to the execution unit, or the data output from the execution unit, to determine whether an operation has occurred. The precharge device for the execution is turned on only when the evaluation indicates that an operation has just occurred. The circuit includes an AND gate whose output controls the precharge device, and whose inputs include one line from the evaluation circuit, and one line for cycling (the system clock).

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. Program instructions in the processor select a second associativity level of a known appropriate level, and implement the second associativity level in the cache using a second mapping function. Application software may provide the program instructions, wherein the application software has procedures that may result in cache "strides" at particular associativity levels, and the known appropriate level is chosen to lessen memory latencies due to strides. Alternatively, the program instructions may be part of an operating system which monitors memory address requests, determines how efficient a procedure will operate at different associativity levels, and selects a most efficient level for the known appropriate level.

Abstract: A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

Abstract: A method of maintaining cache coherency in a multi-processor computer system, which avoids unnecessary writing of values to lower level caches in response to write-through store operations. When a write-through store operation is executed by a processing unit, the modified value is stored in its first level (L1) cache, without storing the value in a second level (L2) cache (or other lower level caches), and a new coherency state is assigned to the lower level cache to indicate that the value is held in a shared state in the first level cache but is undefined in the lower level cache. When the value is written to system memory from a store queue, the lower level cache switches to the new coherency state upon snooping the broadcast from the store queue. This approach has the added benefit of avoiding the prior art read-modify-write process that is used to update the lower level cache.

Abstract: A method and system for introducing flux onto at least one surface of a solder pump achieve their objects as follows. A solder pump nozzle is submerged into a flux reservoir. In response to such submersion, the flux in the reservoir is actively introduced into the solder pump nozzle. In one embodiment, the active introduction is achieved by creating a negative pressure in a solder pump nozzle such that flux fills a vacated volume. The created negative pressure is produced by moving a solder column, contained within the solder pump nozzle, under the influence of an applied electric current and an applied magnetic field.

Abstract: A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy of a value (instruction or data) was the most recently accessed block out of a group of cache blocks in different caches (but at the same cache level) that share valid copies of the value. The "recent" state can advantageously be used to implement optimized memory operations such as intervention, by sourcing the value from the cache block in the "recent" state, as opposed to sourcing the value from system memory (RAM), which would be a slower operation. In an exemplary implementation, the hierarchy has two cache levels supporting a given processing unit cluster; the "recent" state can be applied to a plurality of caches at the first level (each associated with a different processing unit cluster), and the "recent" state can further be applied to one of the caches at the second level.

Abstract: A method of accessing electronic information, by loading an original document onto a data processing system, selecting a link embedded in the original document (wherein the link is associated with a linked document), and creating a new document by merging the linked document with the original document. Other new documents can similarly be created by merging additional linked documents with the earlier new documents in response to the further selection of other links embedded in the new documents. The original document and one or more linked documents can thus be displayed as a single, unitary file, as well as being printed as a single document. The linked document can be merged with the original document in a variety of manners. The invention is particularly useful in accessing hypertext pages on the World Wide Web of the Internet.

Abstract: A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.

Abstract: Provided are a method and system for replacing terminals, linked in a client server relationship with a central server, interacting with hardware specific programs within the central server, and wherein each terminal is identified by hardware specific programs within said central server via specific hardware attributes, and where the specific hardware attributes include at least a port identification and an I/O processor identification associated with the port identification. The method and system achieve the foregoing via the following. A processor is substituted for a selected terminal. Particular hardware attributes of the selected terminal are identified. The identified particular hardware attributes of the selected terminal are emulated using communications software.

Abstract: The present invention relates to the continuous production of coated, dyed, printed, or painted materials by dip coating, spraying or printing in which a plurality of flowable materials including a liquid color concentrate are fed to a continuous mixing chamber with a substantially continuous input and output. The liquid color concentrate is dispensed by a dispensing apparatus including at least a first substantially vertical hollow chamber; a controllable pump device having an inlet fluidly connected to an outlet of said first hollow chamber for pumping the liquid color concentrate to the mixing chamber; a sensor for outputting substantially continuously a signal dependent upon a height of a liquid in the first hollow chamber; and a control device suitable for controlling at least one flow rate determining characteristic of the controllable pump in response to the output signal of the sensor so as to maintain the flow rate of the liquid to be dispensed through the pump device at a predetermined value.

Abstract: A data transmission system generally comprising a bus with transmission lines, and a signal driver that applies a first signal to a first one of the transmission lines, and applies one or more signals to at least one other of the transmission lines which is adjacent the first transmission line, wherein the second signal has an amplitude proportional to an amplitude of the first signal such that crosstalk between the first and second transmission lines is substantially reduced. The signal driver may take the form of a current mode driver, which provides the compensating (second) signal with a current which is k/c times smaller than the current of the first signal, wherein k is the mutual capacitance between the first and second transmission lines, and c is the capacitance between either of the first or second transmission lines and a ground plane. If the first and second transmission lines are orthogonal, the current mode driver preferably includes differential input lines.

Abstract: A method of dynamically avoiding defective cache lines in a cache used by a processor of a computer system is disclosed. A repair mask is used, having an array of bit fields each corresponding to a cache lines in the cache, and certain bit fields in the repair mask array are initially set to indicate that a group of corresponding cache lines are defective. Thereafter the repair mask is updated by setting additional bit fields in the repair mask array to indicate that an additional group of corresponding cache lines are defective. Access to all defective cache lines is prevented based on the corresponding bit fields in the repair mask array. The initial setting of certain bit fields can take place at fabrication of the cache chip in response to testing of the cache lines. Additionally, the repair mask may be updated each time the computer system is booted in response to testing by the boot procedure.

Abstract: Disclosed is an IC card having a connector wherein a socket or a jack can be inserted in a direction that is parallel to the face of the IC card. The connector includes a connector body having a rotatable housing attached thereto. The housing has an opening by which a socket or a jack can be fitted and secured to the connector body. When a socket or a jack is not connected to the IC card, the housing member can lie level along the face of the IC card but when a socket is to be connected, the housing can be raised such that it is almost perpendicular to the face of the IC card. The socket or the jack can therefore be inserted parallel to the face of the IC card.

Abstract: A system for efficiently transferring heat from a cold sink to a hot source utilizing thermoelectric cooling effects is disclosed. A plurality of thermoelectric elements are coupled in a series configuration with a power source. The plurality of thermoelectric elements are coupled in a parallel configuration with the cold sink and the hot source. The surface area of the hot source is greater than the surface area of the cold sink such that the plurality of thermoelectric elements can effectively transfer heat from the cold sink to the hot source in response to the power source. The plurality of thermoelectric can be fabricated on an integrated circuit with analog or digital circuity and effectively cool hot spots.

Abstract: A method and construction for providing thermal management and vibration isolation to a component that requires a controlled temperature during operation. The component (e.g., a hard disk drive) is mounted within an enclosure such that the component is substantially isolated from mechanical vibrations, and the isolation mechanism further provides a thermal path from the component to the enclosure. An elastomeric article which supports the component may be attached to the interior of the enclosure, the elastomeric article being loaded with thermally conductive fillers (fibers or non-directional particulates molded within the elastomer material). Alternatively, a wire rope which supports the component may be attached to the interior of the enclosure, the wire rope having at least one support strand and at least one heat transfer strand that has a higher thermal conductivity than the support strand.

Abstract: A computer network provides distribution of a multithread process among different data processing stations in the network. In one embodiment, a global name server is used to distribute the threads and update values associated with the threads. When the process is created, the global name server establishes a distributed process context by dividing logical addresses used by the process among physical addresses corresponding to respective portions of the system memory devices (RAM) in different data processing stations. The global name server assigns a universally unique identification number (UUID) to each process, and uses the UUID to manage the distributed threads. When the data in the distributed process context is updated, the changes are apparent to all threads executing in the distributed process. This approach simplifies access and retrieval of shared process context information, and may be implemented using current thread models, making it easier to incorporate into existing networks.

Abstract: A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes is then defined using a mapping function which operates on the encoded addresses, such that the program instructions may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The program instructions can modify the original addresses by setting a plurality of programmable fields. Application software may provide the program instructions, wherein congruence classes are programmed based on a particular procedure of the application software which is running on the processor, that might otherwise run with excessive "striding" of the cache.