Abstract: Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be a ball grid array substrate or a metal leadframe. The stack of semiconductor chips is mounted to the substrate. Each semiconductor chip has a plurality of bond pads on an active surface thereof. The bond pads of the first semiconductor chip face corresponding ones of the bond pads of the second semiconductor chip, and are joined thereto through an electrically conductive joint. One of a plurality of bond wires extend from each of the joints to the substrate. Accordingly, pairs of bond pads of the first and second semiconductor chips are electrically interconnected, and are electrically connected to the substrate through the respective bond wire.

Abstract: A multiple die package is formed, which allows multiple die to be interconnected using internal leads or traces from a lead frame. A plurality of slots in the paddle area of the lead frame are created which define the internal signal traces. Then the outer portions of the die paddle area of the lead frame are removed or trimmed to isolate the internal traces from each other and form a plurality of individual internal leads. Multiple die, either stacked, in a planar array, or a combination of the two, are connected to selected internal leads, such as by wire bonding, to form the desired die-to-die interconnections for routing signals between die without interfering with normal wire bond fan-out. A tape can be adhered to the interior portion of the die paddle area prior to trimming to hold the internal traces in place and leave the ends of the traces exposed for wire bonding to the die.

Abstract: A semiconductor package and a method and a substrate for making the package are disclosed. The substrate of an exemplary package includes metal circuit patterns covered by a layer of an insulative nonphotoimageable solder mask material. A plurality of apertures are formed by laser ablation through the nonphotoimageable solder mask layer so as to expose a selected region of at least some of the circuit patterns. A bond wire is electrically connected between a semiconductor chip connected to the substrate and the respective circuit patterns through the laser-formed aperture over the circuit pattern.

Abstract: A method for overmolding a ceramic substrate for a semiconductor chip or other electrical device, and a resulting package, are disclosed. In one embodiment, plural ceramic substrate panels having a matrix of semiconductor chips thereon are precisely located on and attached to a temporary support member using an alignment tool. The member and the attached ceramic substrate panels are then placed in a mold tool. When the mold tool is closed, it clamps down on the member around the ceramic substrate panel, and not on the ceramic substrate panel itself. A mold compound injected into the mold tool encapsulates the chips and ceramic substrate panels. Subsequently, packages each containing a chip are singulated from the encapsulated ceramic substrate panels.

Abstract: A semiconductor package incorporates spacer strips enabling one or more semiconductor dies having central terminal pads to be stacked on top of one another within the package and reliably wire bonded to an associated substrate without shorting of the bonded wires. Each of the spacer strips comprises a flat, elongated strip of an insulative material that mount at edges of a surface of a die such that they straddle the central terminal pads thereon. The die is electrically connected to the substrate by a plurality of fine conductive wires having a first end bonded to one of the central terminal pad on the die, a second end bonded to a terminal pad on the substrate, and an intermediate portion between the first and second ends that passes transversely across the top surface of one of the spacer strips. The spacer strips have spaced pads or grooves on or in their top surfaces that captivate the individual wires and thereby redistribute the wires and prevent them from contacting the die and each other.

Abstract: A vacuum sealed package for a semiconductor chip, such as a micro-electromechanical (MEM) chip, is disclosed, along with a method of making such a package. In an exemplary embodiment, the package includes a ceramic substrate and a lid that together define a cavity wherein the chip is mounted. The substrate includes a conductive (e.g., metal) interconnect pattern that extends, at least in part, vertically through the substrate. I/O terminals are provided on an external surface of the substrate. A vent hole, at least partially lined with a metal coating, extends through the substrate into the cavity. A metal plug seals the vent hole. The vent hole is sealed by placing the package in a vacuum chamber, evacuating the chamber, and heating the chamber so as to cause a metal preform on the substrate to flow into the vent hole and form the plug.

Abstract: Semiconductor chip packages having molded plastic substrates and recessed I/O terminals are disclosed, along with methods of making such packages. In an exemplary embodiment, the molded plastic substrate includes a metal interconnect pattern and a plurality of indentations in a surface thereof. Each indentation may include at least one projection. The indentation and any projections therein are covered by a metal lining. A metal contact, which serves as an I/O terminal, is placed in each of the indentations and is fused to the metal lining thereof. A chip is mounted on the substrate and is electrically connected to the metal contacts by the interconnect pattern. The package further includes a lid or hardened encapsulant over the chip.

Abstract: The invention provides a method and apparatus for electrically connecting the die of a high power semiconductor device to a substrate with a conductive strap such that the connection is resistant to the shear stresses resulting with changes in temperature. In one embodiment, the method includes providing a substrate having first and second portions that are electrically isolated from each other. A semiconductor die having top and bottom surfaces and one or more active electronic devices formed therein is also provided. The device has a first terminal connected to a first conductive layer on the bottom surface of the die, and a second terminal connected to a second conductive layer on the top surface of the die. The first conductive layer is electrically coupled to a top surface of the first portion of the substrate. The second conductive layer is electrically coupled to the second portion of the substrate with a metal strap.

Abstract: Methods of making packages for integrated circuit devices, and in particular for attaching a plurality of integrated circuit die to a substrate strip, are disclosed. The substrate includes a plurality of die mounting sites. A B-staged epoxy film is on each site. An exemplary method includes placing an integrated circuit die on the adhesive film of each site. After a plurality of integrated circuit die are individually placed on the substrate, the adhesive films of a plurality of sites are cured simultaneously in a batch process. The curing permanently attaches the die to the substrate. Subsequently, the die are wire bonded to their respective substrate sites and encapsulated. The encapsulated substrate is cut to form individual packages.

Abstract: A low dropout voltage regulator with non-Miller frequency compensation is provided. The LDO circuit has two wide-band, low-power cascaded operational transconductance amplifiers (OTAs): an error amplifier and a unity-gain-configured voltage follower. The unity-gain-configured voltage follower drives a gate of a power PMOS path transistor with a high parasitic gate capacitance. The wide-band, low-power OTAs enable the use of a single, low-value load capacitor with a low equivalent series resistance (ESR). A frequency compensation capacitor is connected in parallel with the upper resistor of a feedback network, which introduces a zero-pole pair that enhances the phase margin close to unity-loop-gain frequency.

Abstract: Package embodiments for housing an electronic device are disclosed, along with methods of making and interconnecting the packages. The package body may be formed of an injection molded plastic encapsulant. The package body includes a cavity in which the electronic device is contained. A lid extends over the open end of the cavity. Metal leads extend from the package body. A first portion of each lead is at a lower surface of the package body, a second portion of each lead extends vertically adjacent to a peripheral side of the package body, and a third portion of each lead extends over the package lid at a top surface of the package. The package has a key formed in the lid or at the first surface of the package body. The key is adapted so as to engage a corresponding key hole in another package stacked therewith. Abutting leads of the stacked packages form an electrical connection between the packages.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.

Abstract: Stackable integrated circuit packages with pin and barrel interconnects are disclosed, along with methods of making such packages. In an exemplary embodiment, a package includes a molded plastic body, metal coated barrels on an upper side of the body, and metal coated pins on a lower side of the body. The pins are arranged coaxial with respective barrels. An integrated circuit is mounted on the upper side of the body. Metal traces electrically couple the integrated circuit to the barrels. Vias through the body electrically connect the metal coated barrels to respective metal coated pins. Two or more packages may be stacked and electrically coupled together by inserting the pins of a top package into the barrels of a lower package. The pins of the lower package may be soldered to a conventional printed circuit board, or may be mounted on a mounting substrate including corresponding metal coated barrels.

Abstract: A printed circuit board for a semiconductor package, a semiconductor package, and methods for manufacturing the same are disclosed. One printed circuit board includes a core layer with circuit patterns formed thereon. The circuit patterns do not extend to a periphery of the circuit board. Each circuit pattern includes a bond finger and/or an input/output land. A solder mask is provided over the circuit patterns, except for bond fingers and lands. A first metal layer is plated only on the horizontal outer surface of the bond finger and/or ball land of the respective circuit pattern, and not over the remainder of the circuit pattern. The localized plating of the first metal layer enhances adhesion of the solder mask to the circuit patterns, enhances adhesion of an encapsulant to the bond fingers, and avoids waste of the first metal layer material.

Abstract: A package for a device includes a substrate having a common voltage plane and a mounting region. The device is mounted to the mounting region. An electrically conductive dam structure is disposed on the upper surface of the substrate circumscribing the perimeter of the mounting region. The electrically conductive dam structure is coupled to the common voltage plane. An electrically insulating encapsulant at least partially fills the pocket defined by the substrate and the electrically conductive dam structure. The electrically insulating encapsulant contacts the electrically conductive dam structure. An electrically conductive encapsulant overlies the electrically insulating encapsulant and is coupled to the electrically conductive dam structure.

Abstract: This invention provides a method for making a semiconductor package with stacked dies that eliminates fracturing of the upper die(s) during the wire bonding process. One embodiment of the method includes the provision of a substrate and pair of semiconductor dies, each having opposite top and bottom surfaces and a plurality of wire bonding pads around the peripheries of their respective top surfaces. One die is attached and wire bonded to a top surface of the substrate. A measured quantity of an uncured, fluid adhesive is dispensed onto the top surface of the first die, and the adhesive is squeezed toward the edges of the dies by pressing the bottom surface of the second die down onto the adhesive until the two dies are separated by a layer of the adhesive. The adhesive is cured, the second die is then wire bonded to the substrate, and the dies are then molded over with an encapsulant.

Abstract: This invention provides a method apparatus for electrically connecting a semiconductor die, such as a power MOSFET, to a substrate on which the die is mounted, e.g., a lead frame, with a conductive strap, such that the connection is resistant to the shear stresses incident upon it with changes in temperature of the device. The method includes providing a conductive strap, and in one embodiment thereof, forming a recess in the top surface of the substrate. The bottom surface of a flange portion of the strap is attached to the floor of the recess such that the recess captures the flange and prevents relative horizontal movement of the flange and substrate with variations in the temperature of the device. Other embodiments include attaching the strap to the die and substrate with joints of a resilient conductive elastomer, and forming apertures in the strap and substrate that cooperate with a conductive joint material to reinforce the connection against temperature-induced shear forces.

Abstract: A package for one or more semiconductor die is disclosed, along with a method of making the package. In one embodiment, the package includes a substrate having opposed top and bottom surfaces and an aperture therebetween. The substrate includes an insulative layer and top and bottom metal layers on the insulative layer around the aperture. The metal layers are electrically connected through the insulative layer. At least one die is supported within the aperture by an insulative encapsulant material. The bottom surface of the die is exposed. In alternative embodiments, a stack including a plurality of die (e.g., two die) are supported in the aperture. Rectangular metal are provided in a single row on the bottom surface of the substrate along at least two edges of the package.

Abstract: A die mounting apparatus that includes: 1) a die including a bottom surface having an active region is located among the bottom surface and a first and second bond pads provided on the bottom surface outside of the active region; 2) a substrate including a top surface and protruding electrical contacts that are electrically coupled to the first and second bond pads; and 3) a first encapsulant circumscribing a periphery of the die, where the first encapsulant, the bottom surface of the die, and the top surface of the substrate define a free space. The first encapsulant extends inwards from the periphery of the die towards the active region but does not contact the active region. Advantageously, the first encapsulant forms a seal around the die to protect its active region from the environment. A further advantage is that the first encapsulant provides added security that bond pads of the die will remain in contact with contacts formed among the substrate even after distortion of the shape of the die.