Abstract: A semiconductor memory cell for a programmable read-only memory includes a polysilicon layer formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and an isolating diode. Because of the different impurity concentration, the diodes have different reverse-bias breakdown voltages. The programmable diode has the lower reverse-bias breakdown voltage. The high reverse-bias breakdown voltage of the isolating diode has the effect of blocking the parasitic current drain on the programming current.

Abstract: A method of fabricating a thick field oxide isolation layer employs dual photoresist layers and selective ion implantation. A thick field oxide layer is grown on a silicon wafer and is covered with a negative photoresist layer followed by a thicker positive photoresist layer. The positive photoresist layer is exposed through a mask and developed to leave a portion remaining where an aperture in the field oxide is to be made. Boron ions are implanted into the silicon wafer through the layers not covered by positive photoresist. The remaining positive photoresist and the underlying negative photoresist are removed to expose the field oxide, after which the patterned negative photoresist is used as a mask to etch a hole in the field oxide that is self-aligned between the boron implants.

Abstract: A method of fabricating an array of high capacity memory cells comprises patterning a semiconductor surface to form memory cell areas; covering the memory cell areas with insulator; forming an ion layer of first conductivity type throughout the insulator; forming an ion layer of second conductivity type throughout the semiconductor surface; forming a first conductive pattern over the insulating layer to form a storage gate and to define a storage region extending to an isolation region and to define a transfer region spaced from the isolation region by the storage region; removing ions of first conductivity type from the portion of insulator above the transfer region and from other active areas; removing ions of second conductivity type from the transfer region and other active areas; diffusing ions of first conductivity type from the insulating layer to the storage region to produce in the storage region a shallow ion layer of first conductivity type and a deep ion layer of second conductivity type; and form

Abstract: A method of fabricating an array of high capacity memory cells comprises forming a transfer gate over each cell area spaced from an adjacent isolation region to define a storage region in the semiconductor surface between the transfer gate and isolation region and to define a bit line region on the other side of the transfer gate; forming a shallow ion layer of first conductivity type in the storage region self-aligned with the transfer gate; forming a deep ion layer of opposite conductivity type in the storage region self-aligned with the transfer gate; forming a storage gate over a portion of the storage region spaced laterally from the transfer gate to form a gap between the storage and transfer gates; and introducing ions of the first conductivity type into the portion of the storage region defined by the gap to at least neutralize some ions in the deep ion layer.

Abstract: An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.

Abstract: A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

Abstract: A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supply voltage. The transistors have a common substrate.By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.

Abstract: An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

Abstract: In a circuit including a transistor pair feeding separate loads at different load voltages, current gain modulation or Early effect is avoided by employing an operational amplifier to maintain the collector-base voltages of the transistors equal and thereby maintain their alpha current gains equal.

Abstract: Two independent power supplies for an I.sup.2 L or ISL logic array can be timed to turn on at different times by a simple RC network connected externally of the logic array. The differential timing is utilized to condition or set a bistable device in a predetermined initial desired state, without requiring an additional device terminal pin for that purpose.

Abstract: In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits.

Abstract: A single flip flop is integrated with MOS circuitry which enables the single flip flop to be triggered by each of several individual clocked functions without interfering with one another. The flip flop responds only to low to high transitions of each clock signal input. This is accomplished by feeding back the flip flop output to each trigger circuit in such a way as to temporarily disconnect the trigger circuit from the flip flop during the time period between two successive low to high transitions of a particular clock signal, so that the flip flop can be triggered by other clocked functions without interference from the particular clock signal.

Abstract: Selective plasma vapor etching process for performing operations on a solid body formed of at least two different materials capable of being vapor etched exposed at, at least, one surface of the body, with the body being disposed in a chamber having a partial vacuum therein. A gas plasma is created within the chamber to produce active species of atoms and molecules so that these species come into contact with the surface of the body to chemically react at least one of the materials with active species from the gas plasma to form a gas-non-gaseous chemical reaction by controlling the concentration and reaction kinetics of specific species, and by controlling the activation energy of the etching reactions to produce a difference in rates between the materials so that the etching is more selective to one material over the other. The species is also controlled by the frequency of the electromagnetic energy.

Abstract: A protective circuit arrangement for three state bus drivers, incorporating insulated gate field effect transistors, affords protection against short circuiting of the output bus. The protective circuit senses the short circuit condition at the output bus of two push-pull output transistors and feeds back a signal to the input circuit of the ON transistor which reduces the input drive to that transistor and limits the output current through that transistor to a safe value.

Abstract: A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.

Abstract: A temperature compensated piezoresistive transducer includes a silicon body having a major top surface and an under surface. The body has generally parallel spaced first and second elongate slots formed therein extending through said top and under surfaces to define a center portion between said slots and first and second outer portions at the outward edge of the respective slots. The center portion is adapted to receive pressure to be measured. The body has an additional slot extending through the top and bottom surfaces and extending around the first, second and center portions to define the outer periphery of a transducer membrane with portions of the body remaining to integrally support the membrane. Plural piezoresistive elements having elongate and transverse dimensions are formed on the membrane. The elements are arrayed to receive compressive and tensile stress when pressure is applied.

Abstract: The invention relates to a JFET memory in which the information at the gate electrodes of the JFET's is stored and read-out non-destructively. Each JFET has an IGFET structure situated entirely within the JFET and the gate of which is coupled to the source or drain of the JFET. The information can be refreshed periodically at cell level (that is without external amplifiers) by means of said IGFET.

Abstract: A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally parallel to said major surface. Spaced first and second collector regions are carried by said layer. A third one conductivity region is formed in said layer spaced from said first and second region and extending to an exposed surface of said layer. A fourth region of opposite conductivity type is formed within said third region and extends to an exposed surface of said layer. The layer, third and forth regions form the respective regions of an opposite conductivity--one conductivity--opposite conductivity type source transistor.

Abstract: Complementary silicon gate MOS structure formed of a semiconductor body of silicon having a major surface with a first region of N conductivity type formed in the body and extending to the surface and a second region of P conductivity type formed in the body and extending to the surface. A P-channel MOS device is formed in the first region and an N-channel MOS device is formed in the second region to provide complementary devices in the body. Each of the P and N-channel devices has a polycrystalline gate structure in which the polycrystalline material is doped with a P-type impurity to make possible the matching of threshold voltages of both devices.In the method, complementary MOS devices are formed by the use of two separate etching operations on the polycrystalline material and forming relatively thick layers of silicon type material on the semiconductor body in separate operations.

Abstract: A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.