Abstract: A junction field effect transistor and a bipolar transistor are merged in a single composite device disposed within a single isolation region by the use of planar processing techniques. The device includes an annular source region formed within a semiconductor body portion constituting a collector zone. Within the central portion of the collector zone circumscribed by the annular source region there is formed an emitter zone nested within a region that constitutes both the drain region of the JFET and the base zone of the bipolar transistor. An annular channel region connects the annular source region and the central drain region. An annular region forming a semiconductor junction with the annular channel adjacent to the annular source region constitutes one of two gate regions of the JFET. The other gate region is constituted by the body portion serving as the collector zone.

Abstract: Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

Abstract: A metal contact system for an IGFET having shallow source and drain includes a refractory metal silicide layer forming low resistance ohmic contact to a silicon surface, a layer on the silicide layer of another refractory metal to serve as a barrier against diffusion of the interconnect metal, and a layer of interconnect metal over the diffusion barrier layer. The refractory metal layers are deposited by sputtering platinum or platinel for the first layer and titanium-tungsten for the second layer. In metal gate construction an additional layer of chromium is used as an etch resistant mask to protect the refractory metal layers from chemical attack when removing silicon nitride after it has been used initially as an oxidation mask and later as a sputtering mask.

Abstract: A semiconductor transducer chip is flip-chip bonded to a semiconductor interface chip, which is mounted on the ceramic package. Thermal coupling between the package and the transducer chip is minimized by the small contact area between the transducer chip and interface chip. Micron size spacing between the spring membrane in the transducer chip and the interface chip produces squeeze film damping of the spring membrane.

Abstract: A random access memory (RAM) in which each memory cell includes a JFET having two gate electrodes selectable by means of a single word line and a single bit line. The JFETs have a common electrode formed from the substrate of a semiconductor body common to each of the memory cells, which serves as one of the main electrodes of each of the JFETs.

Abstract: JFET memory structures, in particular for RAM's with non-destructive reading-out of the charge state of a floating gate electrode in which the primary selection is realized by means of capacitive coupling with the floating gate electrode. The secondary selection takes place on one of the main electrodes of the JFET structures in which the other main electrode can be connected to the supply. By means of a second common gate electrode the pinch-off voltage of the channels can be adjusted so that the channels are non-conductive in the non-selected condition and a good detection of the information state is obtained in the selected condition.

Abstract: In an integrated circuit, a semiconductor body having a surface, spaced semiconductor circuits formed in the body, intercoupling means formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

Abstract: A bipolar memory cell of reduced size requires only four I.sup.2 L operated transistors and three access lines. Two current injection transistors supply operating current to two inversely operated flip-flop transistors and also function as load devices as well as coupling devices. The three access lines conduct power to the cells as well as the signals for the write and read operations. A write operation is performed by ratioing the currents supplied to a memory cell array such that only a selected cell is written.

Abstract: A binary to multistate line driver and remote receiver includes a line driver comprising first and second injection logic encoder circuits. The circuits have current injectors and are connected to receive respective first and second binary signals to provide analog outputs at a signal output terminal in response to the input signals. The encoder circuits each have current injectors with substantially similar structural characteristics. The line driver further includes a reference channel circuit connected to a reference terminal to provide a reference to the encoded signals. The reference circuit has a current injector with structural characteristics substantially similar to the encoder circuit current injectors.

Abstract: A high density semiconductor structure and method is disclosed including a semiconductor body of one conductivity having a substantially planar surface. A first region of one conductivity is formed in the body and extends to the surface. A layer of opposite conductivity is interposed between the first region and the body said layer having relatively thin and uniform walls which extend to separate the first region from the body. At least one opposite conductivity region is formed entirely within the first region and extends to the surface. An opposite conductivity region is formed in the body and overlaps a portion of the layer. Lead means are provided for contacting each of the respctive regions and the body. The collector-up injection logic structure thus formed requires little or no surface area for the injection source transistor.

Abstract: A high speed monolithic A/D converter utilizes a strobed comparator, low level differential logic and thin film resistor integrated circuit processing. The A/D converter is of the successive approximation type and quantizes 10 bits at a 5 megasample rate.

Abstract: An etching process for patterning cermet thin film resistors includes the provision of a layer of molybdenum over the cermet layer to provide a good adherent surface for a photoresist layer subsequently deposited thereon. After the photoresist and molybdenum layers are patterned in separate steps, the cermet is preferentially etched with hot phosphoric acid to produce the desired cermet resistance pattern.

Abstract: A ramp generator for driving a bar graph display which utilizes a feedback circuit to set its maximum level of the ramp.

Abstract: A controlled thermal expansivity structure whose length along a given axis of the structure and thermal expansivity in the direction of the axis, i.e. total change in length in response to a given temperature change, are independently adjustable in a manner which permits adjustment of the structure in length while maintaining its thermal expansivity constant and adjustment of the thermal expansivity of the structure while maintaining its length constant. The range of thermal expansivity adjustment may include zero expansivity to permit adjustment of the structure to dimensionally stable mode. The described structure is a load-bearing strut with end fittings which are adjustable to vary the length and thermal expansivity of the strut.

Abstract: An elastic strain energy deployable helical antenna having a tubular resiliently flexible antenna element of relatively flat oval cross-section fixed at one end to a support and formed into a normally extended, resiliently compressible helix with the major axis of the oval cross-section of the element substantially normal to the longitudinal axis of the helix, and flexible tension members of shorter overall length than the fully extended length of the helix fixed at one end to the support and extending axially of the helix across and secured to its helical turns. The antenna helix is compressible axially to a contracted length for storage and is deployable axially by stored elastic strain energy to an extended operating length at which the tension members are stressed in tension by the helix to reinforce the latter against deflection laterally of its longitudinal axis. The tension members may have rigid portions between the helix turns for increasing the natural frequency of vibration of the antenna.

Abstract: A vertical dipole antenna for the ELF (extremely low frequency) range. The antenna provides a series resonant circuit consisting of an inductor and the distributed capacitance of the conductor such as a wire which may be carried by lighter-than-air craft. The lighter-than-air craft may be conductive, in which case it contributes to the capacitance or the capacitance may be solely represented by the wire. The antenna may be frequency or phase modulated. In case of frequency modulation the frequency of the generator must be changed accordingly so that the series resonant circuit remains resonant at the frequency to be radiated. The antenna can be readily moved. A plurality of antennas may be provided to form a super-radiant array.

Abstract: A laser of the type which generates linearly polarized light and including optical means for self-alignment. Among such polarized lasers are, for example, solid state lasers and particularly ruby lasers, as well as various gas lasers employing Brewster windows. The problem is solved by utilizing a corner reflector in the laser cavity which generates two parallel laser beams. In order to achieve effective laser operation the polarization determining aspect of the laser, that is the crystal axis or Brewster windows, must be so oriented with respect to the corner reflector that the laser beam in passing through the laser is so reflected by the corner reflector that the light will return through the laserable material with the same directon of polarization as that of the original laser beam generated by the laser.

Abstract: A universal differential line driver with a single pair of outputs provides by means of a pair of control input lines selectively sourcing, sinking or high impedance conditions on the output pair.

Abstract: A microwave bandpass filter of the coupled bar type providing either an interdigital or combline structure. The filter consists of a plurality of resonator sections having two ground planes and a resonating bar integral with the structure and extending perpendicularly from one of the walls and parallel to the ground planes. The spacer sections match the dimensions of the resonator sections, but may have different widths thereby to control the spacing between adjacent resonator bars. Alternate resonator sections and spacer sections are mechanically interconnected to form a filter of the desired electrical properties.

Abstract: A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.