Abstract: A method for forming a bottom electrode of a capacitor is provided. A substrate having a conductive region is provided. A first insulation layer, a stop layer and a second insulation layer are formed on the substrate in order. The first insulation layer, the stop layer and the second insulation layer are patterned to form an opening. The opening exposes the conductive region in the substrate. A first conductive layer is formed on the second insulation layer and fills the opening, and then the first conductive layer is defined to form a plug and a metal plate. The plug can be electrically connected with the conductive region. The metal plate is used as a mask, and the second insulation layer is removed by anisotropic etching to form a third insulation layer having a first distance from the third insulation layer surface to the stop layer surface.

Abstract: A method to form a shallow trench isolation (STI) structure includes forming a trench on a semiconductor substrate. Then a channel stop is formed under the trench. A pad oxide layer and a silicon nitride layer are sequentially formed over the substrate. A side-wall spacer is formed over the silicon nitride layer on each side of the trench. An oxidation process is performed to oxidize the side-wall spacer. Another side-wall spacer and oxidation are repeatedly performed until the trench is filled with oxide. An oxide layer is formed over the substrate. Then an active ion etching process is performed to remove the layers above the substrate other than the trench region. The STI structure then is formed.

Abstract: A screw with two cut removing curved grooves has a head and a shank with a helical threads. The shank has two lengthwise grooves partially overlapping with each other, when viewed projectively from the horizontal surface or from the vertical surface of the center line or axis of the screw.

Abstract: On a substrate with a number rows of gates are formed. After a metal silicide layer is formed above the gates, a silicon-rich layer is formed. The silicon-rich layer is either a further metal silicide layer, with a higher silicon concentration or a pure silicon layer.

Abstract: An encapsulation method of organic electroluminscence device is provided. An organic electroluminescent device is formed on an indium-tin-oxide glass substrate. A metal electrode is formed on the organic electroluminescent device. The organic electroluminescent device is encapsulated by a nitride layer or a carbide layer formed by using segmental sputtering at a low temperature. The substrate is soldered on a metal plate and covered by a metal cap.

Abstract: A video communicating equipment that receives digital image data and a clock signal as input, generating analogue image data internally and then outputting the analogue image data to a computer screen. The video communicating equipment comprises a line buffer, a complex programming logic device and a digital-to-analogue converter. Using only a normal telephone network and an ordinary computer screen, the video communication equipment of this invention enables both voice and video communication functions. Furthermore, the computer screen can be selected to output either computer images or video communication images.

Abstract: A method of fabricating a semiconductor device using a Salicide process to increase the surface area of a polysilicon gate is described. First, a polysilicon layer is formed over a substrate. A mask layer with an opening is formed on the polysilicon layer. A mask spacer is formed on the sidewalls of the opening. Part of the polysilicon layer under the opening is removed with the mask spacer and the mask layer serving as a mask. An insulating layer is formed in the opening. The mask spacer and the mask layer are removed. The polysilicon layer that is not covered by the insulating layer is removed. The insulating layer is removed to expose the surface of the remaining polysilicon layer, wherein a groove is formed on the surface of the remaining polysilicon layer. Then a Salicide process is performed to form a metal silicide layer on the substrate and the remaining polysilicon layer.

Abstract: A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride layer is formed on the oxide layer. The silicon nitride layer, the oxide layer, and the first dielectric layer are patterned to form a dummy gate structure. A spacer is formed on a sidewall of the dummy gate structure. The spacer and the dummy gate structure together form a dummy gate. An ion implantation step with the dummy gate serving as a mask and a thermal annealing step are performed to form a source region and a drain region on opposite sides of the dummy gate in the substrate. A second dielectric layer is formed next to the spacer. A top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure. The silicon nitride layer is removed. A nitridation process is performed to convert the oxide layer into a nitride layer.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: A method of fabricating a DRAM capacitor. After forming a node contact opening in a dielectric layer on the substrate, a conductive layer having an annulus hollow is formed. A recess is formed on the conductive layer and a spacer is formed on the sidewall of the spacer, after which the annulus hollow is filled with an oxide layer. A photoresist layer for defining the capacitor region is formed. The etching stop layer, the oxide layer, and the spacer are removed to form the bottom electrode. Then, the dielectric layer and the upper electrode are formed in sequence.

Abstract: A lead frame structure can prevent the warping of a semiconductor package body. The lead frame has a downset die pad and upset internal leads so that packaging material can be evenly distributed both above and below the lead frame.

Abstract: An alignment strategy for asymmetrical alignment marks in a wafer, in which the positions of the a symmetrical alignment marks are determined twice. A first set of positions is detected after a chemical-mechanical polishing step. A second set of positions is detected after a rotation in which the wafer is rotated by 180.degree. in the plane of the surface of the wafer.

Abstract: A signal converter with a dynamically adjustable reference voltage according to the invention, which can receive different qualities of signals. The signal converter includes an input circuit and a reference voltage generator. The input circuit converts a first digital signal, such as a GTL+ signal, into a second digital signal, such as a TTL or CMOS signal, based on an adjustable reference voltage generated by the reference voltage generator. When a control circuit needs to receive the first digital signal from outside via the input circuit, the control circuit can adjust the reference voltage by controlling the reference voltage generator so as to receive the first digital signal with a different quality.

Abstract: A method of improving selectivity between silicon nitride and silicon oxide. A pad oxide is formed on a substrate. Using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, a silicon nitride layer is formed on the silicon oxide layer. The silicon nitride is implanted by boron ions to transform into boron nitride. A conventional method is performed to form a shallow trench isolation.

Abstract: A method for monitoring dosage/focus/leveling is provided. A control wafer is provided and divided into several regions. Five of the regions near the center of the wafer are used to monitor normally. Other regions are used as dummy shots. When a situation of a stepper changes greatly, the dosage/focus/leveling of the control wafer is monitored using the dummy shots. In monitoring exposure dosage, the middlemost region is monitored. One of the five regions, which is the most central, is exposed with a low exposure energy to enhance sensitivity of critical dimension versus energy. Many points with small areas are developed in the centermost region to take sufficient samples. Since the developed points are close, effects from the nonuniformity of development and from the nonuniformity of the photoresist layer are prevented. In focus/leveling monitoring, a curve diagram of exposure dosage versus critical dimension is provided. An exposure parameter is taken at a range of the curve with a large slope.

Abstract: A surface treatment method for bonding pad is described, in which a passivation layer is formed on a bonding pad and an opening is formed within the passivation by a plasma etching process. The bonding pad is corroded by the etching plasma containing fluorine during the etching process. The bonding pad is rinsed with deionized water comprising carbon dioxide to reduce the effects of the corrosion phenomenon.

Abstract: A method for forming a shallow-trench isolation starts with forming a polysilicon layer, which has less stress, as the mask layer for patterning the trench on a provided substrate. An oxide layer is then formed to cover the polysilicon layer and fill the trench. The oxide layer is then removed by first performing a chemical mechanical polishing process to remove a portion of the oxide layer, wherein the remains of the oxide layer still covers the polysilicon layer and fills the trench. After that, an etching back process is performed to remove the oxide layer from the top of the polysilicon layer to form the oxide plug, which is used as an isolation.

Abstract: A self-aligned contact process for fabricating semiconductor devices on a semiconductor substrate is described. The present process comprises providing two gates structure on a semiconductor substrate, wherein the gate structure comprises a gate and a passivation layer on the top surface thereof. A buffer layer is conformally overlaid on the gate structure, passivation layer and the semiconductor substrate. A photoresist material is formed on the semiconductor substrate to a level between the top surface of the passivation layer and interface between the passivation layer and gate. The buffer layer is removed to the level of the photoresist layer. Next, the photoresist material is removed. A spacer is formed on the sidewall of the buffer layer and the passivation layer of the gate structure. An insulating layer is formed on the semiconductor substrate and then, a contact opening is formed therein to expose the semiconductor substrate.

Abstract: A delay circuit is provided to dynamic random-access memory (DRAM) for use to assist the measurement of the DRAM charge/discharge period, which allows the DRAM charge/discharge period to be more precisely measured. In measurement, a plurality of such delay circuits are chained together to allow the charge/discharge period measurement to be performed in a collective manner on all the DRAM cells in the delay chain circuit, which can be then used to determine the charge/discharge period of each DRAM cell. When the charge or discharge process on the DRAM cell in the current stage is completed, the DRAM-cell delay circuit of the current stage will likewise generate an output voltage of a certain logic state to trigger the next stage to undergo a charge/discharge process. Furthermore, a large-current output driving circuit is coupled to the last stage in the delay chain circuit to allow an increased output driving capability.

Abstract: A broad-band microstrip antenna implemented using a dielectric base as its main body is disclosed. The base has two sides where the dual-mode resonator is located on the first side, while the grounded plane is located on the second side of the dielectric base. The dual-mode resonator has a high-frequency resonator and a low-frequency resonator, which are partially positioned in parallel. Due to the electric-magnetic effects, these two resonators are mutually coupled to significantly increase the operating bandwidth. In addition, there is a feed line on the first side of the dielectric base, which connects to the dual-mode resonator to provide signal transmission. In addition, there is a grounded mask in the antenna, which is located on the first side of the dielectric base, to provide sheltering for the feed line, and connect to the grounded plane to form a closed area to provide a more complete radiation field pattern.