Abstract: A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor.

Abstract: A method of manufacturing interconnects disclosed in the invention comprises the following steps. First, a substrate having an insulator formed thereon is provided. A first dielectric layer having a first conductive section and a second conductive section formed therein, is formed on the insulator. A second dielectric layer is formed over the substrate and covers the first conductive line and the second conductive line. A via hole is formed in the second dielectric layer to expose parts of the first conductive section and the second conductive section and the part of the first dielectric layer therebetween. The part of the first dielectric layer between the first conductive line and the second conductive line is removed until the insulator is exposed, thereby forming a coupling hole. And, a plug is formed in the via hole and the coupling hole, wherein the plug is electrically coupled to the first conductive section and the second conductive section.

Abstract: A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, after scanning the water mark by a defect inspection machine, the performance of the wafer product is evaluated.

Abstract: An earphone-microphone set that has a pair of adjustable ear braces. The earphone-microphone set includes an earphone housing for enclosing the earphone. There is a shallow groove around the outer edge of the housing and a cable latch positioned vertically at each end of the groove. A hole is also drilled beside each of the cable latch. A microphone capable of rotating is attached to the earphone housing. One end of a signal transmission cable is connected to the earphone. The cable comes out from the edge of the earphone housing around its mid-section. The other end of the cable is connected to a plug. An upper ear-brace-adjusting pin and a lower ear-brace-adjusting pin are inserted into the respective upper circular hole and the lower circular hole beside the cable latches. The upper and the lower ear-brace-adjusting pin also passes through an upper ear brace and a lower ear brace so that each ear brace can slide up or down independently.

Abstract: A method is described for manufacturing shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer, a trench penetrating through the mask layer and the pad oxide and into the substrate and a first liner oxide layer in the trench. A portion of the first liner oxide layer is stripped away to expose the bottom corner of the mask layer. A portion of the mask layer is stripped away to expose the top corner of the first oxide layer. The first liner oxide layer is removed to expose the surface of the trench. A second liner oxide layer is formed on the sidewall and the base surface of the trench and the trench is filled with an insulating material to form a shallow trench isolation.

Abstract: A method for manufacturing an interconnect. A substrate having a first dielectric layer and a barrier layer formed thereon is provided. A plurality of conductive wires is formed on the barrier layer. A second dielectric layer is formed on the barrier layer exposed by the conductive wires, wherein the second dielectric layer has a surface level between the top surfaces and the bottom surfaces of the conductive wires. A spacer is formed on each portion of the sidewalls of the conductive wires exposed by the second dielectric layer, wherein there is a gap between two adjacent spacers. The second dielectric layer is removed. A third dielectric layer is formed on the conductive wires, the spacer, the sidewalls of the conductive wires and the portion of the barrier layer exposed by the conductive wires and fills the gap to form an air cavity between the conductive wires under the spacer.

Abstract: An installation can adjust gas supply in a reaction chamber according to the conditions in the reaction chamber. The installation comprises sensors, a gas-supplying panel and a driving device. The sensors are located in the reaction chamber to sense the conditions in the reaction chamber. The gas-supplying panel has a plurality of apertures, which are asymmetrically located, through which apertures gas is supplied. The driving device, coupled to the sensors and the gas-supplying panel, drives the gas-supplying panel to respond to the conditions sensed by the sensors, in which the gas-supplying panel can adjust the positions of the gas supplied through the apertures.

Abstract: A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region.

Abstract: A method of manufacturing a shallow trench isolation alignment mark comprises the steps of first providing a silicon wafer whose surface has an alignment mark formed thereon. Next, a silicon nitride layer is formed over the silicon wafer, and then shallow trenches are formed. At least one of the shallow trenches is positioned at a distance of about 2000 .ANG. to 10000 .ANG. from the edge of the alignment mark. Thereafter, an oxide layer is formed over the silicon nitride layer, and then a chemical-mechanical polishing operation is conducted to remove a portion of the oxide layer and silicon nitride layer above the alignment mark. Altogether, a layer of silicon nitride having a thickness of about 600 .ANG. is removed from the top of the alignment mark. Finally, the silicon nitride layer is also removed. By forming a shallow trench at a distance of between 2000 .ANG. to 10000 .ANG.

Abstract: A wide-angle zoom lens includes four sets of lenses. The first set of lenses has a negative effective focal length. The second set of lenses has a positive effective focal length for changing the focal length of the wide-angle zoom lens. The third set of lenses has a negative effective focal length for changing the focal length of the wide-angle zoom lens, as well. The fourth set of lenses has a positive effective focal length. The focal length of the wide-angle zoom lens can be changed by changing the positions of the second set of lenses and the third set of lenses along the optical axis of the wide-angle zoom lens.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.

Abstract: A method for manufacturing the capacitor of a dynamic random access memory cell. The method includes the steps of first providing a substrate having field effect transistors thereon, and then forming a dielectric layer over the substrate. Next, a contact opening that exposes the source/drain region is formed in the dielectric layer, and then conductive material is deposited over the substrate, filling the contact opening to form a conductive layer. Thereafter, the conductive layer is patterned, and then a portion of the exposed dielectric layer is removed to form trenches that surround the conductive layer. In the subsequent step, conductive spacers are formed on the sidewalls of the trenches and the conductive layer. The conductive spacers and the conductive layer form the lower electrode structure of a capacitor.

Abstract: A steam cooking system for cooking foods such as a light Chinese dish called as dim sum with steam comprises a steam generator disposed outside a guestroom of a restaurant, a cooking chamber formed adjacent to each of tables in the guestroom, and a steam line extending from the steam generator to at least one steam outlet formed in a bottom of the cooking chamber. A valve is provided in the steam line at the vicinity of the steam outlet to be switchable between an open position of supplying steam into the cooking chamber and a close position of stopping the supply of steam. A control unit controls the valve to keep the valve at the open position for a cooking time period determined according to a menu to be cooked with steam. An exhausting unit is formed at a top of the cooking chamber to exhaust used steam from the cooking chamber to the outside of the guestroom.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: A method of manufacturing a CMOS. A substrate is provided, wherein the substrate has a first conductive-type well, a second conductive-type well, an isolation structure formed therein, a first gate electrode on the second conductive-type well and a second gate electrode on the first conductive-type well. The first conductive-type well and the second conductive-type well are partly isolated from each other by the isolation structure. A first offset spacer is formed on a sidewall of the first and the second gate electrodes and a second offset spacer on a sidewall of the first offset spacer, wherein a portion of the first offset spacer extends on a surface of the substrate and the second offset spacer is on the portion of the first offset spacer. A first LDD region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the second offset spacer.

Abstract: An apparatus and a method of producing a dual ion/electron source. The ion beam and the electron beam are produced by a charged particle optical system. Using an ion source metal to emit an ion beam or an electron beam. The direction of the ion beam and the electron beam is identical. Neither the particle source nor the sample need to be rotated or shifted.

Abstract: A method for manufacturing a metal-oxide-semiconductor (MOS) transistor is described. In the invention, doped regions of the local pocket type are formed in the substrate after the source/drain terminals of a MOS transistor in the logic circuit area are formed. The method includes the steps of forming an insulation layer over the entire substrate. Then, a portion of the insulation layer is removed to expose the spacers on the sidewalls of the gate electrode. Subsequently, the spacers are removed, and then an ion implantation operation is conducted to implant dopants into the substrate through the windows formed by the uprooted spacers. Ultimately, doped regions of the local pocket type are formed in the substrate under the lightly doped drain source/drain terminals of a MOS transistor.