Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: There is disclosed an adaptive equalizer filter with a current splitting system for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.

Abstract: There is disclosed, for use in an analog to digital (ADC) converter, an ADC stage that receives a differential analog input signal, quantizes the differential analog input signal to a plurality of digital bits, and generates an output residue signal corresponding to a quantization error of the differential analog input signal.

Abstract: For use in a processor having integer and floating point execution cores, logic circuitry for, and a method of, converting negative numbers from floating point notation to integer notation.

Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous.

Abstract: There is disclosed a differential difference amplifier for amplifying an input signal close to a negative supply voltage and adding an offset voltage to the amplified input signal. The differential difference amplifier comprises: 1) a first non-inverting input terminal coupled to the input signal; 2) a first inverting input terminal coupled to the negative supply voltage; 3) a second inverting input terminal coupled to a feedback resistor coupled to an output of the differential difference amplifier; and 4) a second non-inverting input terminal coupled to the offset voltage.

Abstract: There is disclosed a differential current mirror system and method for providing differential output current signals that are proportional to differential input current signals in which common mode current signals are rejected. The system comprises a pair of diode connected transistors and a differential amplifier. The pair of diode connected transistors comprises a first and second transistor coupled together. The differential amplifier comprises a third and fourth transistor coupled together in a differential amplifier configuration. The gate of the third transistor receives a first input current signal from the drain of the first transistor and the gate of the fourth transistor receives a second input current signal from the drain of the second transistor.

Abstract: There is disclosed a system and method for current splitting for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.

Abstract: A cache has programmable, finely ganular, locked-down regions within a way or way(s) so that the contents of the locked-down regions are not evicted. The finely granular locked-down regions need not be contiguous and are programmed as either "locked-valid" or "locked-invalid" to provide general purpose memory that is local and private to the processor or for masking defected cache lines or portions thereof. Finely granular, programmable spatial regions of the cache that are locked-down are preferably, although not exclusively, programmed through two additional states to the standard MESI (Modified, Exclusive, Shared, Invalid) protocol for multipurpose cache coherency.

Abstract: Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift and rotate circuit, a 2-bit shift and rotate circuit and a 4-bit shift and rotate circuit. For double word sized (32-bit) operands, the variously sized shift and rotate circuits may be selectively enabled to perform between 1-bit and 31-bit shift/rotate/pass operations. For byte sized operands, the 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range, i.e., 1-bit to 7-bit, of possible shift/rotate operations.

Abstract: A system and method of virtualized audio generation and capture in a computer system is disclosed employing the native central processing unit and a system management mechanism, to generate and capture music and other sound effects, responsive to events occurring in an application program executed by the native central processing unit or to input buffer percentage full signals.

Abstract: For use in an x86-compatible processor having a cache, a circuit and method for setting a size of the cache and a computer system employing the circuit or the method. In one embodiment, the circuit includes: (1) multiple access circuitry dividing the cache into separate physically-addressable sectors and (2) sector disabling circuitry, coupled to the cache, that selectively allows at least one of the sectors to be disabled to decrease the size of the cache.

Abstract: A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.

Abstract: A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes). are also disclosed.

Abstract: A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

Abstract: A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the device channel region, and a gate insulator separating the device gate and channel region. The first and second diffusion regions are electrically connected to a positive power supply, and the device gate is electrically connected to a negative power supply. The decoupling capacitor may be formed proximate a signal driver in the integrated circuit. The decoupling capacitor may be formed without additional, expensive semiconductor fabrication steps and operates to minimize noise in the circuit.

Abstract: A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

Abstract: For use in an x86-compatible processor capable of executing MMX.TM. instructions calling for partitioned data to be shifted or routed, an integrated routing and shifting circuit, a method of operation and a computer system containing the same. In one embodiment, the circuit includes: (1) a lower shifter that receives partitioned data therein and shifts at least a first portion of the partitioned data as a function of a received control signal and (2) an upper shifter/router, coupled to the lower shifter and having partitioned input lines and partitioned output lines, that receives the partitioned data from the lower shifter into the source register and selectively shifts or routes at least a second portion of the partitioned data as a function of the received control signal while transferring the partitioned data from the partitioned input lines to the partitioned output lines.