Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.

Abstract: An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal.

Abstract: Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away).

Abstract: A sequencer for use in a pipeline architecture includes circuitry for determining whether the previous instruction was a conditional jump instruction and whether the condition was met, circuitry for determining whether the current instruction is a conditional jump, and circuitry inhibiting a branch responsive to the current instruction, if the previous instruction was a conditional jump and the condition was met. Additionally, circuitry may be provided for treating a CALL instruction as a one-cycle unconditional jump if the preceding instruction was a conditional jump and the condition was not met, thereby implementing a two-cycle IF-THEN-ELSE instruction.

Abstract: A parity circuit generates an output parity bit responsive to a plurality of data input bits. The parity circuit comprises a plurality of transistor stages coupled to the input bits and the output bit, the value of the input bits defining at least one charging path through the transistor stages. The charging path is coupled at first and second nodes to a power supply, such that the charging path is supplied with current at both ends, thereby increasing the responsiveness of the parity circuit.

Abstract: An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Abstract: An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit.

Abstract: A current source suitable for use as a loop filter in a phase-locked loop having two aspects of automatic gain control one for prohibiting the voltage controlled oscillator from stopping as the input voltage approaches the limits of the oscillator and another to compensate for current limiting drain to source voltage drops.

Abstract: An arithmetic circuit 10 for performing prescaled division uses a rectangular multiplier 16 and accumulator 30 operable to calculate a short reciprocal and scaled dividend and divisor to enable the sequential iterative calculation of large radix quotient digits. Each quotient digit can be calculated using a single pass through the rectangular multiplier 16 and accumulator 30 and can be accumulated to form a full precision quotient in a quotient register 36.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: An integrated circuit extraction tool includes an elongated base having a first end and second end. A first set of teeth are provided on the first end and a second set of teeth are provided on the second end. The first set of teeth are spaced at a first spacing distance and the second set of teeth are spaced at a second spacing distance. In the preferred embodiment, the first set of teeth are spaced to correspond with the spacing between pins of a integrated circuit to be extracted and the second set of teeth are spaced at a distance to correspond to the spacing between base portions of a socket's connectors. One or both of the ends may be angled at ninety degrees to allow integrated circuit removal with minimal clearance.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first and second clocks are alternately enabled by a control signal initiated under program control of the external test system.

Abstract: A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

Abstract: A data compression/decompression processor (a single-chip VLSI data compression/decompression engine) for use in applications including but not limited to data storage and communications. The processor is highly versatile such that it can be used on a host bus or housed in host adapters, so that all devices such as magnetic disks, tape drives, optical drives and the like connected to it can have substantial expanded capacity and/or higher data transfer rate. The processor employs an advanced adaptive data compression algorithm with string-matching and link-list techniques so that it is completely adaptive, and a dictionary is constructed on the fly. No prior knowledge of the statistics of the characters in the data is needed. During decompression, the dictionary is reconstructed at the same time as the decoding occurs. The compression converges very quickly and the compression ratio approaches the theoretical limit. The processor is also insensitive to error propagation.

Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Abstract: Rotate circuitry operable to perform rotate operations on various size operands including preconditioning circuitry (10) for duplicating an operand a predetermined number of times to form a preconditioned word. The rotate operation is performed by shifter (22) which shifts the preconditioned word by a specified number of bits. For rotate through carry operations, Cy bit of the carry flag is inserted in the preconditioned word prior to shifting.

Abstract: A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.

Abstract: An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.