Abstract: This disclosure relates to a system and method for realizing asynchronous sequential circuits in a manner analagous to the stored state method for synchronous sequential circuits. The circuit is a stored state circuit including a memory and an output register with an input line and an input request line coupled to the memory and the output register having an output data line and an output acknowledge line. A pulse generator is coupled to the input request line so as to generate a timing signal, for transmission to the output register, a fixed period of time after receipt of a request signal on the input request line. A request signal will not appear on the input request line until a data signal on the input data line has stabilized. Furthermore, an acknowledge signal will not be generated until a signal on the output data line has stabilized.

Abstract: In an approximate content addressable storage system data words are stored in a two dimensional storage array with each data character therein stored in a particularly associated storage row and each data word individually and sequentially character-by-character stored column-by-column. In searching the array for a particular word each storage row associated with a character in the search word is accessed in a manner biased to that character's position in the search word so that the search for all characters occurs effectively in parallel. A searched for character located in its proper position is given maximum value with decreasing value accorded to searched for characters detected one or more positions removed from the proper position in the search word. The value derived for each character is totalled with similar values derived from all other characters in the search word thus arriving at a value indicative of the approximateness of a stored word with the search word.

Abstract: The present disclosure describes a connector or socket having particular application for LSI/VLSI integrated circuit (IC) packages with cylindrical interface pins. The connector is characterized by the ease with which the IC package may be inserted therein or withdrawn therefrom, despite the large number of pins involved. In achieving this result, the connector utilizes a unique contact design wherein two opposing cantilever type spring members include respective contoured fingers for capturing and firmly holding an IC package pin during normal circuit operation. The connector also incorporates one or more contact release plates, each having a plurality of cam-like apertures operatively positioned with respect to the connector contacts. Actuation of a release plate moves each pair of contact spring members toward each other, thereby opening the area enclosed by the fingers and providing substantially zero force package insertion or withdrawal conditions.

Abstract: The invention is a multipart continuous form having several plies and a means to securely fasten the plies which prevents longitudinal slippage. To achieve this result the form has a series of locking and connecting tabs cut along its edge. The locking tabs fasten the inner plies of the form to the connecting tab, thereby preventing longitudinal shifting.

Abstract: An apparatus is provided, for use in an impact printer, in which printer it is required that an impact producing hammer, or assembly of such hammers, be operable in more than one location, whereby the hammer or assembly of hammers is moved between operational positions, the operation of the hammer or assembly of hammers is inhibited except when correctly positioned for operation, any mispositioning of the hammer or assembly of hammers is automatically corrected, wear, introduced by movement of the hammer or assembly of hammers, is minimized, and high operational speed, of the printer, is attained.

Abstract: The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective word is addressed in main memory. The mask memory is made up of multiple bit mask memories each cooperating with one of the redundant memory levels. Each bit-mask memory has multiple sub-memory units which use a randomness technique to store the addresses of defects in main memory.

Abstract: In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Abstract: The present disclosure describes a low insertion force connector for use with integrated circuit (IC) packages of the LSI/VLSI type. The connector is characterized by simplicity of design and economy of manufacture. The well known friction-type contact comprised of members which enclose and bear against the pin surface is replaced by a pin-receiving cup loosely fitted in a cavity in the connector body and supported by one extremity of a light spring member. The opposite extremity of the latter may include an integral tail section or a separate solder or wire wrap tail may be affixed thereto. The force required to seat the IC package in the connector is a function of the spring compressive forces and may be made quite low. Removal force for the package is virtually zero. Additionally, a ramp section in the connector is adapted to receive a wedge-like member which bears against the outer surface of the IC package and causes the gradual collapse of the contact springs as the package is seated.

Abstract: This disclosure relates to a wafer scale power interconnect system by which defective circuits on the wafer can be automatically disconnected from the power and ground lines supplied to each of the circuits. The disconnect device employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be destroyed by an excessive current thereby opening the gate. The disconnect device may also be just such a fuse or a current limiter.

Abstract: In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.

Abstract: Novel apparatus for transferring magnetic and conducting toner from a dielectric surface to plain paper by interposing a dielectric belt mechanism between the dielectric surface of an imaging drum and a plain paper substrate such that the toner is first transferred to the dielectric belt and subsequently transferred to a plain paper in a fusing station. Operably associated cleaning and discharging of the dielectric belt is provided.

Abstract: The present disclosure describes an hermetically sealed integrated circuit package capable of accommodating high density circuit configurations with their attendant high power levels. In performing this function, the package permits the back-bonded integrated circuit chip or die to be mounted to a thermally conductive member of the package which is disposed in an open air stream. Moreover, the opposite side of the package positioned in proximity to the interconnection medium remains available to be fully populated by a large number of closely spaced input/output pins.

Abstract: The present disclosure describes a dressing finger assembly of advanced design for use on automatic wiring machines. Such machines make solderless wrapped electrical connections on pluralities of planar disposed terminals. A dressing finger is employed to form predetermined wire patterns in conjunction with a wrap tool which makes the actual connection. It has been observed that the design of dressing fingers used in present day machines is such that the insulation of the wire being wrapped may be pinched and cut, thereby necessitating its replacement to avoid electrical shorting. In accordance with the present invention, the assembly comprised of a newly designed finger and supporting guide, provide the required retention and support of the wire during wrapping while eliminating the aforementioned damage to the wire.

Abstract: An electronic circuit is described for providing a low current DC supply at increased voltage with high efficiency and minimal hardware complexity. In performing its function, the circuit preferably utilizes a plurality of CMOS voltage-controlled solid state switches in conjunction with a sequenced clock pulse train to implement a compact capacitive-type multiplier. Thus, capacitors are charged in a predetermined order and the charges stacked upon one another to ultimately charge an output storage capacitor to a voltage level which is substantially a desired multiple of the supply voltage applied to the circuit. For descriptive purposes, the present inventive techniques are applied herein to the design for an octupler.

Abstract: An error detecting unambiguous multi-segmented indicia display method and apparatus is disclosed wherein an "OFF" segment is illuminated differently than an "ON" segment of the display to verify that the "OFF" segment is indeed "OFF" and not a malfunctioning "ON" segment. In the preferred embodiment a pulsating voltage is supplied to the "OFF" segments to provide a lower integrated average voltage and therefore a lower brilliance of display. In an alternate embodiment a contiguous "OFF" segment of one color is provided next to each "ON" segment so as to indicate unambiguously that each non-illuminated "ON" segment is in fact indicating "OFF".

Abstract: The present disclosure describes a multi-layered integrated circuit package especially suited for high density circuit applications, such as those involving LSI or ULSI. The package is characterized by short uninterrupted electrical circuit paths between the integrated circuit chip and an interconnection medium. The use of metallized vias or feed-throughs commonly employed in multi-layered packages have been eliminated. Also, heat dissipation is enhanced by the short thermal path between the chip and the outer package surface. Finally, the signal lead configuration permits the area occupied by the package on the interconnection medium to be significantly less than that of present-day packages having approximately the same number of input/output pins or terminals.

Abstract: An N phase digital inverter for converting an input DC voltage level to an output DC voltage level interposes between the input and output terminals thereof a plurality of N parallel switching circuits, each switching circuit thereof comprising in series a power switch and a transformer. The output of each transformer is coupled through a diode to a common point for filtering to generate the output DC voltage. The output DC voltage is sensed and fed to a logic generator for generating a ring sequence of pulses which activate sequentially each power switch in the plurality thereof. The logic generator controls the ratio of pulse time ON divided by pulse time ON plus pulse time OFF to maintain a desired level of output DC voltage.

Abstract: The present disclosure describes a side-loading wire wrapping assembly comprised of a specially configured bit and sleeve, for use on semi-automatic wiring machines. Such machines are used to make solderless wrapped connections on terminals emanating from a common plane. The wire wrapping assembly in present use on many of such machines consists of a fixed sleeve substantially enclosing a spring-loaded bit. The arrangement necessitates front-loading of the bit by the operator--a procedure which is tedious and time consuming. The present invention obviates these difficulties by converting the fixed-sleeve assembly from front-loading to side-loading. This is accomplished by providing in the sleeve, a wire feed aperture in contiguity with a longitudinal slot and of orienting the former with a widened portion of the slit formed in the bit periphery by the wire receiving bore.

Abstract: A zero clearance, backlash free, adjusting mechanism wherein a multithreaded helical member is constrained against movement within a movable support by means of oppositely disposed concentric threaded members separated by a concentric torsion spring. Opposite ends of the torsion spring are captivated by respective opposite concentric members. One of said members being fixidly, slidably mounted within said movable support. Rotation of the helical member forces the two concentric members apart along the helix forcing the members into a zero clearance position effective to prevent any wobble or yawing movement of the helix and thus eliminating any backlash along the helical member. A U-shaped clip surrounds the movable support so as to retain the assembly effective to prevent accidental dislodgement or movement of the concentric members.

Abstract: A self configuring track controller for a diverter gate motor in a stacker area of a document sorting system having pockets in which documents are selectively directed includes identical devices for governing each diverter gate motor in the stacker area. Integral with each track controller is a data line using binary, serial signals to teach each track controller its sequential position in the stacker area relative to other track controllers.