Abstract: In a Foster-Seeley discriminator circuit having a discriminating resonance circuit, resonance circuits having series resonance characteristics are respectively connected between a signal source and both ends of the discriminating resonance circuit so as to raise the level of a composite output voltage of the frequency discriminator circuit, whereby the sensitivity of the output voltage versus the frequency can be enhanced.

Abstract: In a named data processing system, user ownership and verfication of data records is secured by assigning an unique record name to each data record, providing error checking covering both the data record and its associated record name, storing the data record, its associated record name and check code, and requiring the data record name to be provided in order to initiate a fetch operation. Further, the check code enables upon fetching, a verification that an incorrect data record was not inadvertantly fetched due to hardware or other failures. The association of a unique data name with each data record provides for self-descriptive data records thereby permitting the reconstruction of directories which describe the contents of various actual physical locations within an Input/Output system when such directions are lost or otherwise corrupted by hardware or other malfunctions.

Abstract: A method of laminating a cover layer for flexible circuits which provides increased flexibility. The cover layer encapsulates a flexible circuit having a plurality of spaced conductors on a flexible insulating substrate. The cover layer is a tri-layered laminate having a first layer of insulating film, a second intermediate layer of a thermosetting adhesive, and a third layer of a phenolic resin adhesive. The cover layer is bonded to the flexible circuit with the third layer of phenolic resin adhesive being contiguous the conductors.

Abstract: A high speed modular masking circuit having utility in field extraction, bit checking, and other like operations includes a plurality of input address lines for receiving binary numerical representations, two control lines, and a plurality of output masking lines, the number of output lines being equal in number to two raised in power to the number of input lines. When both control lines are at the same binary logic level, that level is likewise present on all output lines. When otherwise, a number of contiguous ones or zeroes are present on the output lines starting at the first output line, the number of ones or zeroes being equal to the binary numerical representation present at the input address lines and the number being either ones or zeroes depending upon the logic levels present on the control lines. The modular masking circuit is adaptable to various embodiments suitable for SSI, MSI, and LSI.

Abstract: The present disclosure describes a device for checking the dc characteristics of electronic nets disposed for example in assemblies utilized in data processing equipment. The operation of the analyzer assumes the presence of one or more controlled impedance nets, as may be achieved through the use of current mode logic configurations. The device which is employed while the circuit under test is in a power-off condition, first determines which type of net is being tested, passes a current of known magnitude through the net, and then compares the actual voltage developed thereacross with expected voltage values falling within a tolerance range. The voltage corresponding to the nominal impedance of the net and the tester current passed therethrough, lies at the center of the range. The analyzer automatically checks all the pins of a monolithic integrated circuit chip in sequence. If the nets associated with all the pins fall within the tolerance ranges, a "good" indication occurs upon test completion.

Abstract: A method of data communications for use in systems employing serial transmission techniques in a ring or loop configuration. Access to the communication network is via a communications processor and a interface unit termed a node. The communications processor is responsible for network protocol and activities as well as for interfacing devices to the network. The node provides the only connection to the loop and drives the clock for the communications processor as well as the node itself from the transmitted data. All information in the communication network is transmitted in a modified Mauchly format and will appear as n-bit data or control characters. A binary ONE is represented as a signal level transition from one level to another, while a binary ZERO is represented by an opposite signal transition. A control character, which always precedes a data character, will either be the address of a node or a null.

Abstract: In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.

Abstract: A large number of terminals are connected to a central computer in a loop utilizing a very high speed transmission medium. A sequential stream of message blocks are provided for transmission by the loop. Each message block includes a first portion specifying a terminal address, and a second portion for specifying information data. Each terminal interrogates the address portion of each message block and responds to its own address by either reading the data portion of the message block or loading into the data portion messages to be transmitted. By generating a continuous stream of message blocks, one for each terminal, and using a randomizing scheme for address generation, it is possible to connect a large number of terminals to a data communications system while maintaining a reasonable response time.

Abstract: High speed electrostatic document handling apparatus wherein an electrostatic charge is deposited on an item-document such as a check and wherein the charge is caused to interact with an electrical field through which the item is obliged to move effective to selectively divert the item into a desired receiving pocket or bin and/or stack the item in the pocket or bin in the original selection order.

Abstract: In accordance with the present disclosure, the conventional metal backplane utilized for mounting and interconnecting electronic components is reinforced to increase its rigidity and permit its acceptance of a large number of closely spaced electrical contacts without excessive deformation when accepting the mating contacts. Such reinforcement is achieved in a manner which does not sacrifice the obstruction free area on the backplane required for terminal interconnection as might be performed by wire wrap techniques or a printed circuit backplane.

Abstract: The present disclosure describes a wire guide for use with a manually operated wire wrap gun. Such guns are used to make solderless wrapped connections on terminals emanating from a circuit board. The wire guide of the present invention is especially useful with multi-spindle guns, such as the dual spindle gun utilized for simultaneously wrapping both wires of a twisted pair or miniature coaxial cable. The present wire guide which is fastened to the sleeve portion of the gun, permits the operator to front load the gun quickly and reliably by directing the multiple wires into the respective wire feed openings of the wrapping tool bits housed within the sleeves.