Abstract: An invalidation buffer is associated with each cache wherein either multiple processors and/or multiple caches maintain cache coherency. Rather than to decode the addresses and interrogate the cache directory to determine if data requested by an incoming command is in a cache, the invalidation buffer is quickly checked to determine if the data associated with the requested data has been recently invalidated. If so and if the command is not intended to replace the recently invalidated data, then the tag and data array of the cache are immediately bypassed to save precious processor time. If lower level caches maintain the same cache coherency and are accessed only through an adjacent cache, then those lower level caches may also be bypassed and a cache miss can be directed immediately to memory. In a multiprocessor system, such as NUMA, COMA, SMP, where other processors may access different cache levels independent of the adjacent cache level, then each invalidation buffer is checked.

Abstract: A circuit is disclosed which adjusts the phase of a signal within an LC sinusoidal or a ring or other capacitive oscillator. The circuit uses FETs as capacitors. The gates of the FETs are connected to the capacitive node of the oscillator. The variable voltage source changes the state of the FET from depleted to inverted mode or from inverted to depleted mode which in turn dramatically changes the capacitance of the FET. The change of state exists for only a few clock cycles, typically less than five cycles, so that only the capacitance within the oscillator is instantaneously affected which changes adds as incremental/decremental frequency to adjust only the phase of the oscillation frequency. In this fashion, the average oscillation frequency not affected.

Abstract: A method and apparatus is disclosed which enhances the integrity of transmitted data or detects when random data is being received which might indicate that a receiver or a transmitter is open or that random data is otherwise being transmitted. A stream of data transmitted in packets having an error code associated with each packet is received into a receiver. The receiver has an error code checker to check the error code of each packet to determine if the data packet has been transmitted error-free. The results of the error checks for n sequential packets are stored in a shift register or counter. An incoming packet then undergoes an error code check and the results of the previous n sequential packets are considered. If a predetermined number of the previous n sequential packets has a transmission error n, then the method decides to reject or accept the error packet based on the quality of data integrity.

Abstract: A feedback mechanism is provided to a current mode differential driver by connecting the center tap of a terminator of the output of the driver through feedback resistors to the gates of a positive and a negative current source connected to the driver. Connecting the center tap between the feedback resistors, the average common mode voltage at the output of the differential driver is substantially constant which avoids variations and reflective noise in high speed data transmission that can occur because of manufacturing tolerances.

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time.

Abstract: A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail.

Abstract: An optical transceiver with a transimpedance amplifier generates a dynamic common mode voltage of the peak-to-peak output current of the photodetector for use as an in-situ optical power meter. Peak-to-peak voltage signal are imposed on the common mode voltage so optical power measurements are obtained using preexisting electrical contacts. An nfet and a capacitor of the transimpedance amplifier smooths the peak-to-peak voltage to create the control signal for the common mode voltage. The common mode current is mirrored into a bank of pfets at the output stage to create a current sink. Depending upon the potential of the common mode voltage, more or less current will be drawn from the peak-to-peak voltage signals output from a final differential amplifier stage of the transimpedance amplifier.

Abstract: A bracket/collar is disclosed to circumscribe an integrated circuit card into an electrical or an optical connector. The bracket/collar has several features, such as grooves, to hold the circuit card into the bracket; the grooves may be on any available edge not mating with or held by the connector, and may hold a corner or other feature of the circuit card. Another feature of the bracket/collar is a mechanism, such as a hook or notch, to connect with the connector. Yet another feature of the bracket/collar is that, by its shape, it provides sufficient loading of the circuit card into the connector so that when dropped or otherwise mechanically shocked, the circuit card is not displaced from its connector. The bracket/collar is especially useful to secure DIMM memory cards within their electrical connectors in handheld computers.

Abstract: The efficiency of an overall computer communications system is greatly improved by a new method to transfer data on a data communications bus. The method allows one or more small command structures of a smaller size to have priority in bus arbitration; and then allow normal bus arbitration to permit large data transfers, such as DMA read operations. Thus, the method balances the need to keep I/O devices utilized, which devices would otherwise experience latency because they are waiting for the larger DMA read operations to conclude. But by allowing a configurable number of these smaller operations to proceed and then permitting larger data transfers to occur, both the host bus and the I/O bus are efficiently utilized.

Abstract: A digital data waveform is precompensated for attenuation through a transmission medium. First, during actual initial power-on or upon reconfiguration of a digital communication system, attenuation characteristics of the transmission medium are actually measured. The attenuation characteristics can be measured by measuring the length of the transmission medium, measuring the error rate of test packets having known frequency, measuring the slope of a test pulse at two separate threshold voltages, and/or measuring the error rate of a random signal packet. Upon determination of the magnitude of the attenuation characteristic, one of a plurality of registers corresponding to the range of values of the attenuation characteristic is selected. These registers have a plurality of pre-emphasis coefficients to be applied in the driver to each bit of a series of digital signal pulses as determined by the transition history of at least three sequential bits.

Abstract: A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

Abstract: A multichip module subassembly is disclosed which provides for a heatsink, a thermal interface, a module cap upon which a multichip module is mounted, a land grid array interposer, and an assembly cover. The module cap has shimmed load posts and adjustable brackets for precise alignment and loading of the interposer onto the module. The cover may have a springplate for precise preloading of the interposer onto the multichip module for transportation. The multichip module subassembly is easily used as a field replaceable unit.

Abstract: An improved and much simplified method to access data banks in a memory system which provides the option of opening more than one bank in a single command. This is especially useful to achieve bursts of data across bank boundaries in a memory system of synchronous dynamic random access memory cards having fast memory bus speeds. The method decodes signals to generate a single command which may open one or more memory bank at a time. Logic can increment the banks, decrement a bank counter, and, if necessary, increment/decrement a row and/or uniquely address a column so that continual data bursts can be achieved seamlessly across bank boundaries in synchronous dynamic random access memory systems. The data banks may be opened all at once, or can be opened sequentially in a staggered manner according to a synchronous or asynchronous, with respect to the memory clock, time delay During that time delay a nop command or a chip deselect command may execute.

Abstract: A computer system and method for use with the computer system to dynamically adapt to a data structure layout other than its own. The data may be an incoming data stream from outside or may be stored within its main memory. Between the transmitting and the receiving CPU there must be an understanding of the conceptual level and format of the data which is transferred. A prefix word in which details of the data structure layout is encoded is generated. The prefix word is appended to the data and transmitted to another CPU or used by the same CPU. Upon receipt of the data, the prefix word is read and decoded and the receiving CPU can dynamically adapt to details of the data structure layout in order to use the data which was generated and transmitted in a heretofore unknown data structure layout.

Abstract: An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas.

Abstract: A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.

Abstract: An improved and much simplified method to address memory space having multiple memory banks in memory such as those in computer systems. The method provides absolute addressing and treats the memory as one large memory but logically divides the memory into banks. Data is not stored consecutively. Bank select logic reads the address bits that are of higher order than the size of the smallest memory bank. Address generation logic reads those address bits that are of lower order than the size of the selected bank.

Abstract: A circuit of a dual control voltage-controlled ring oscillator is disclosed having significantly less power and area while still maintaining a large frequency range and tune accuracy. The dual control ring oscillator has at least two delay paths which can be added or interpolated according to an interpolation variable set by a coarse tune and a fine tune code. In addition, moreover, each of the delay paths have a number of variable delay elements which are varied in response to another input code. When the variable delay elements are capacitors, the capacitance will be varied in accordance with another coarse tune code. In the preferred embodiment, the input codes are digital and the frequency range obtained can be greater than two to one. First, the variable delay elements are adjusted to obtain coarse tuning of the dual control ring oscillator then the interpolation variable is more finely adjusted to obtain fine tuning of the ring oscillator.

Abstract: An electronic circuit and a method of designing the electronic circuit having conductive fill stripes which are electrically attached to the power distribution or to the signal routing of the circuit. Preferably, the conductive fill stripes are electrically attached to the power distribution and are interspersed between the power buses and signal wires on the various metal layers to satisfy the metal density requirements of integrated circuit and chip manufacturing. The conductive fill stripes are added during the design process after the placement of the power distribution and signal routing so that electrical continuity between the conductive fill stripes and the connecting bus, metal density requirements, other design rules and logic verification can be completed as the rest of the chip is designed.

Abstract: The constant current source circuit provides current that compensates for changes in performance resulting from changes of temperature. The circuit mixes variable amounts of current having a negative temperature coefficient with current having a positive temperature coefficient. Analog and digital embodiments of the circuit are disclosed. In the analog embodiment, the amount of current having a positive temperature coefficient is added to an amount of current having a negative temperature coefficient as determined by the voltage difference between a variable control voltage input to transistors and a bandgap reference voltage.