Patents Represented by Attorney, Agent or Law Firm Karuna Ojanen
  • Patent number: 5880900
    Abstract: A disk drive apparatus and a method for executing an error recovery process for an error caused by thermal asperity is set forth by positioning a disk read/write head in the vicinity of a thermal asperity and then by vibrating the head so that the head hits the foreign matter or protrusion on the surface of the disk causing the thermal asperity. Vibrations in the longitudinal direction are generated in a head by supplying a vibration signal to VCM. The vibration signal is superimposed on a head driving signal. During the vibration process, the head is positioned on a track shifted from a thermal asperity causing track by several tracks in order to hit the thermal asperity by an edge of a head.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: March 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: Kenji Okada, Koichi Arai, Hisashi Kakuta, Hiroaki Suzuki, Masakazu Sasaki, Akira Kibashi, Tatsuya Endo
  • Patent number: 5875346
    Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventor: David Arnold Luick
  • Patent number: 5873512
    Abstract: A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: James Daniel Bielick, Mark Kenneth Hoffmeyer, Phillip Duane Isaacs, Thomas Donald Kidd, David Allen Sluzewski
  • Patent number: 5844910
    Abstract: An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: December 1, 1998
    Assignee: International Business Machines Corporation
    Inventors: Hideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue
  • Patent number: 5806753
    Abstract: A method of forming a bond structure for use with integrated circuits and semiconductor electronics and carrier assemblies is disclosed. Metallurgical paste is screen printed through a stencil and the stencil is left in place during the reflow process. The melting point of the bond structure and the metallurgical paste is lower than the melting point of interconnects on the electronic components and less than the decomposition temperature of the carrier assemblies to which the electronic components are bonded.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: September 15, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Daniel Bielick, Mark Kenneth Hoffmeyer, Phillip Duane Isaacs, Thomas Donald Kidd, David Allen Sluzewski
  • Patent number: 5734816
    Abstract: A nonvolatile memory with flash erase capability includes a plurality of clusters each having a plurality of sectors, each of the sectors holding the attribute information for identification. A cluster information sector is placed at the top of a cluster to which it belongs. A data sector is placed in a data area which is the region other than the top of the cluster. A controller connected to the nonvolatile memory creates a cluster information copy sector when erasing a cluster, and reconstructs cluster management information from the cluster information copy sector when initializing a cluster, thereby forming a cluster information sector. Accordingly, endurance against failure such as power failure in a solid state file apparatus using the nonvolatile memory is improved.
    Type: Grant
    Filed: March 10, 1994
    Date of Patent: March 31, 1998
    Assignee: International Business Machines Corporation
    Inventors: Hideto Niijima, Takashi Toyooka
  • Patent number: 5712580
    Abstract: A linear phase detector used with half-speed quadrature clock architecture is provided. The linear phase detector includes a first circuit receiving a data signal, a first half-speed quadrature clock signal and a second half-speed quadrature clock signal. The first circuit generates an adjusted data signal and a polarity representing signal of the first half-speed quadrature clock signal. A high speed phase detector is coupled to the first circuit for generating a linear phase correction signal.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: January 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Matthew James Paschal
  • Patent number: 5664145
    Abstract: Described is a technique for transferring data between a device controller and a device in a data storage subsystem. The controller has a data buffer through which passes data being transferred to and from the device. The controller communicates with the device by means of low level multi sector Read/Write orders and the data requested by the controller is transferred between device and controller in the form of 32, 64 or 128 byte packets. The device has a relatively small data buffer which can store one packet of data at a time. While one order is executing on the device, the controller is able to issue subsequent orders. One of these orders is an EXTEND order which orders the device to continue reading beyond the data specified in the read order currently executing on the device. The EXTEND order also allows implementation of `back to back` writes.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: September 2, 1997
    Assignee: International Business Machines Corporation
    Inventors: Norman Apperley, Patrick Allen Buckland
  • Patent number: 5661382
    Abstract: A circuit to drive a brushless motor which consumes less power because it uses pulse width modulation. The invention has at least two loops; one loop to control the switching of transistors in a push-pull configuration drives current in the different coils of the motor when those transistors connected to ground are driven in a linear, rather than a saturated, mode. This loop also incorporates a soft switching waveform shaping circuit which slowly switches the phase current so that the electromagnetic noise of the motor does not enter the magnetic head on the disk. The other loop actually controls the speed of the motor based on the linear mode of the transistors.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: August 26, 1997
    Assignee: International Business Machines Corporation
    Inventors: Ken Enami, Satoshi Yamamoto
  • Patent number: 5659447
    Abstract: Method, with structure, of production of precision head/disk interfaces for near contact recording in a low viscosity liquid lubricant film. Triangular shaped bearing pads in an assembled hard drive are brought to bear upon a rotating lubricated disk to dislodge, smooth and polish any residing asperity. The triangular shape of the bearing pads sweeps away and directs to the outer edge of the disk any of the remaining fine carbon sputtering debris which is loosened as the bearing pads are drawn from the inner dimension to the outer dimension of the disk.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Thomas Allen Gregory, Christopher Guild Keller
  • Patent number: 5646802
    Abstract: A reduced height disk drive includes a suspension-actuator assembly in which a head suspension (10) is attached to an actuator (9) on the same side of the head suspension as a transducer head (8) is attached to the head suspension for writing and reading information on and from a disk (7). A spin motor cable (17) is located on the outside of a housing (2) and connected to pins (14) extending from the housing through pins (18) extending from the housing and lines (16) contained in the housing. A printed circuit board (3) having a through hole (3e) in which a connector (13) is provided connects to pins (14) extending from the housing. A flexible printed circuit inside the housing has a connector (11k) for connecting to the pins (14) and (18) at one end and a fixing member for mechanically attaching to the pins at the other end. The flexible printed circuit is attached to the pins in a folded condition.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: July 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Akiyama, Akihiko Aoyagi, Kazuhiko Takada, Hitoshi Tsujino
  • Patent number: 5634007
    Abstract: A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: May 27, 1997
    Assignee: International Business Machines Corporation
    Inventors: Salvatore A. Calta, Robert B. Cook, Fernando A. Luiz, Gregory M. Nordstrom, Martin W. Sachs, Caryl A. Thorn
  • Patent number: 5625636
    Abstract: A monolithically integrated optoelectronic device is provided which integrates a vertical cavity surface emitting laser and either a photosensitive or an electrosensitive device either as input or output to the vertical cavity surface emitting laser either in parallel or series connection. Both vertical and side-by-side arrangements are disclosed, and optical and electronic feedback means are provided. Arrays of these devices can be configured to enable optical computing and neural network applications.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: April 29, 1997
    Inventors: Robert P. Bryan, Peter Esherick, Jack L. Jewell, Kevin L. Lear, Gregory R. Olbright
  • Patent number: 5617430
    Abstract: An electronics systems having variable interconnections among major components is tested by dynamically identifying the locations and types of all system components at the time the test is to be performed, for building a global model describing the interconnections among these components. Specific tests appropriate for this model are then dynamically generated and executed. Data on the components themselves identifies them. The tests employ boundary-scanning techniques to locate failing drivers, receivers, and bidirectional driver/receivers, as well as open and shorted interconnections.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: April 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Angelotti, Wayne A. Britson, Steven M. Douskey, Kerry T. Kaliszewski, Michael A. Weed
  • Patent number: 5586331
    Abstract: An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: December 17, 1996
    Assignee: International Business Machines Corporation
    Inventor: Sheldon B. Levenstein
  • Patent number: 5584033
    Abstract: A plurality of devices attached to a communications bus observe a burst transfer protocol which allows pausing only at pre-determined, fixed intervals of n data words, where a word is the width of the bus. In accordance with this protocol, once burst transfer is initialized the sending device transmits an uninterrupted stream of n data words over the communications bus, after which either the sender or receiver may cause transmission to pause. The sender may need to wait for more data, or the receiver may need to finish processing the data just received. The pause lasts as long as needed until both devices are ready to proceed. This cycle is repeated until the data transmission is complete. The sending and receiving devices do not relinquish control of the bus during a pause, and therefore are not required to re-initialize communications.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: December 10, 1996
    Assignee: International Business Machines Corporation
    Inventors: Wayne M. Barrett, Bruce L. Beukema, William E. Hammer, Daniel F. Moertl
  • Patent number: 5572659
    Abstract: An adapter connected between a host computer and disk storage devices provides interfaces for connecting to the host computer and the disk storage devices having the same interface design. The adapter itself includes control means for building a redundant disk storage system. Moreover, the adapter itself includes means for detecting and indicating a failed disk storage device, means for replacing the failed disk storage device, and means for rebuilding a redundant disk storage system after the replacement of disk storage devices. A command is configured so that the host computer can have access to each of disk storage devices for maintenance purposes. The adapter makes it easy to configure a highly reliable redundant disk storage system for a small computer system without any change to existing hardware or software.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: November 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Iwasa, Hideo Asano, Yutaka Shimizu
  • Patent number: 5566305
    Abstract: An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventor: Sheldon B. Levenstein
  • Patent number: 5552950
    Abstract: A direct access storage device includes at least one disk mounted for rotation about an axis and having opposed disk surfaces for storing data. A magneto-resistive (MR) transducer head is mounted for movement across each respective disk surface for writing to and for reading data signals from the disk surface. Each MR transducer head includes a write element and a read element. A preamplifier, associated with the MR transducer head, amplifies read and write signals of the read element and the write element. A flex cable couples the read and write signals between the preamplifier and the MR transducer heads. The flex cable includes a common read return signal line for each sequential pair of the MR transducer heads.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Jerome T. Coffey, Dale E. Goodman, Joe M. Poss
  • Patent number: 5550690
    Abstract: A clamp for securing one or more data storage disks to a hub is formed as a slightly frusto-conical shaped annulus of resilient material with inwardly and upwardly extending lobes that are displaced radially outward during installation about a hub. Clamping force is derived from the compression of the lobes which are captured by the hub and the twisting of the annulus from the frusto-conical configuration to a substantially radial orientation. The clamp is formed of a material that is softer than the disk to cause the clamp to be compliant and conform to the disk irregularities and thereby avoid compromising disk flatness. The clamp component material composition is also modified to achieve a coefficient of linear expansion that is identical to the disk. The outer periphery of the clamp presents an interrupted flange that permits a tool to engage the clamp, perform the assembly about the hub and be disengaged using automated equipment.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: August 27, 1996
    Assignee: International Business Machines Corporation
    Inventors: Zine-Eddine Boutaghou, Randy J. Bornhorst, Douglas W. Johnson