Abstract: An electronic device according to one embodiment of the invention includes at least a first memory element and a second memory element, a first plurality of initialization value sets, and a second plurality of initialization value sets. The device further includes first and second initialization logic circuits that receives a mode value and a reload signal. Upon occurrence of the reload signal, the first initialization logic circuit selects a first predetermined initialization value set from among the first plurality of initialization value sets according to the mode value and initializes the first memory element with the first predetermined initialization value set. Substantially simultaneously, the second initialization logic circuit likewise selects a second predetermined initialization value set according to the mode value and initializes the second memory element.

Abstract: Ring access control circuitry comprises a receive interface, a host interface coupled to the receive interface, a mate interface coupled to the host interface, a flow control agent coupled to the mate interface, a transmit interface coupled to the flow control agent, and a wrap path coupled from between the flow control agent and the transmit interface to between the receive interface and the host interface. A wrap is initiated over the wrap path in response to a link failure. The ring being controlled could be a resilient packet ring.

Abstract: An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: A facsimile system is disclosed for transferring a facsimile using a Transmission Control Protocol/Internet Protocol (TCP/IP) network. The facsimile system comprises a first communication processing system and a second communication processing system. The first communication processing system converts the facsimile into application packets that indicate individual application packet lengths. The first communication processing system then converts the application packets into TCP/IP packets and transfers the TCP/IP packets to the TCP/IP network. The second communication processing system receives the transferred TCP/IP packets from the TCP/IP network and converts the transferred TCP/IP packets into transferred application packets. The second communication processing system converts the transferred application packets into the facsimile using the individual application packet lengths.

Abstract: Packet processing circuitry comprises a look-up engine and a processor. The look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM. The look-up engine retrieves a first context structure based on the first result. The look-up engine builds a summation block using the first context structure and transfers the summation block. The processor receives and processes the summation block to control handling of the communication packet.

Abstract: An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.

Abstract: A link layer controller comprises a network layer interface, a physical layer interface, and a memory controller. The network layer interface exchanges packets with the network layer system and transfers a status signal to the network layer system. The physical layer interface exchanges the packets with the physical layer system. The memory controller exchanges the packets with the network layer interface, a memory, and the physical layer interface. The memory controller also generates the status signal to indicate available space in the memory.

Abstract: Packet processing circuitry comprises a processor and a look-up engine. The look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM. The look-up engine generates a second selector based on the first result. The look-up engine transfers the second selector to the CAM and receives a corresponding second result from the CAM. The look-up engine retrieves a first context structure based on the second result. The look-up engine builds a summation block using the first context structure and transfers the summation block to the processor. The processor receives and processes the summation block to control handling of the communication packet.

Abstract: Data (e.g. legacy LAN traffic) segmented into packets provide a header and a cell payload for each cell in each packet. The cell payloads are transferred to a region address in a host memory in accordance with determinations by a control memory. When the cell payload is to be transmitted from the host memory, the cell payload for a particular region address is combined with the header stored in the control memory for such address. Streaming data (e.g. voice or video) occurs at a regular rate and is not necessarily broken into packets. The streaming data is segmented to provide cell headers and cell payloads. The cell payloads are then transferred to a host receive FIFO in accordance with a determination by the control memory and are stored in a data sink. Cell payloads from a data source are transferred into a host transmit FIFO at a particular rate and are transferred from the host transmit FIFO preferably at a substantially constant rate higher than the particular rate.

Abstract: A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.

Abstract: Packet processing circuitry comprises a processor and a look-up engine. For a first communication packet, the look-up engine transfers a first selector to a CAM and receives a corresponding first result from the CAM, retrieves a first context structure based on the first result and builds a summation block using the first context structure, transfers the summation block to the processor, writes a second selector to the CAM and receives a corresponding second result from the CAM, and writes the summation block to a memory location corresponding to the second result. For a second communication packet, the look-up engine transfers the second selector to the CAM and receives the corresponding second result from the CAM, retrieves the summation block based on the second result and transfers the summation block to the processor The processor receives and processes the summation block to control handling of the first and second communication packets.

Abstract: Circuitry to free the core processor from performing the explicit read operation required to read data into the internal register set. The processor's register set is expanded and a “shadow register” set is provided. While the core processor is processing one event the “context” and “data” and other associated information for the next event is loaded into the shadow register set. When the core processor finishes processing an event, the core processor switches to the shadow register set and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the “context” and “data” associated with the next event before the current event ends. In this case, the core processor still starts processing the next event and the pre-fetch continues during the event processing.

Abstract: An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer.

Abstract: Packet processing circuitry comprises a look-up engine and a processor. The look-up engine transfers a selector to a CAM and receives a corresponding result from the CAM. The look-up engine retrieves a context structure from a context memory based on the result and transfers the context structure to the processor. The processor receives and processes the context structure to control handling of the communication packet. The processor modifies the context structure and transfers the modified context structure to the look-up engine. The processor generates an update instruction and transfers the update instruction to the look-up engine. The look-up engine receives the update instruction and the modified context structure. The look-up engine automatically writes the modified context structure to the context memory in response to the update instruction.

Abstract: A content-addressable memory is comprised of processing logic and selector logic. The processing logic receives a first selector including packet header information from the packet processing circuitry. The processing logic transfers the first selector to the selector logic. The processing logic generates additional selectors and transfers the additional selectors to the selector logic. The selector logic receives and processes selectors for matches and provides results corresponding to the matches. The processing logic receives the results from the selector logic and transfers at least some of the results that point to packet processing context structures to the packet processing circuitry.

Abstract: A packet communication scheduling system comprises tunnel schedulers, a packet scheduler, and a rate controller. The packet scheduler generates a packet schedule and first-set information in response to packet information. The first tunnel scheduler generates a first schedule for a first set of tunnels in response to the first-set information. The first tunnel scheduler also generates second-set information in response to the first-set information. The second tunnel scheduler generates a second schedule for a second set of tunnels in response to the second-set information. The second tunnel scheduler also generates third-set information in response to the second-set information. The third tunnel scheduler generates a third schedule for a third set of tunnels in response to the third-set information. The third tunnel scheduler selects a next third-set tunnel identifier based on the third schedule.

Abstract: An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.

Abstract: An integrated circuit processes communication packets and comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.

Abstract: A signaling technique for use with an asynchronous transfer mode (ATM) over asymmetric digital subscriber line (ADSL) system is disclosed. The ATM over ADSL system employs an ATM multiplexer (MUX) operatively connected to a number of downstream ATM devices and operatively connected to an upstream ATM switch. The MUX is configured to receive and process upstream setup messages that originate from the downstream ATM devices. In response to an upstream message cell, the MUX compares the call reference number (CRN) contained in the setup message with a table of CRN values associated with other calls. If necessary, the MUX assigns a new CRN value to the current setup message such that the current connection with the originating downstream device is uniquely identified by the assigned CRN. The MUX uses a CRN mapping table to facilitate the unambiguous downstream routing of subsequent signaling cells.