Asynchronous transfer mode system for, and method of, writing a cell payload between a control queue on one side of a system bus and a status queue on the other side of the system bus
A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.
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This application is a continuation of U.S. patent application Ser. No. 08/764,692, filed Dec. 11, 1196, now U.S. Pat. No. 6,057,790, which is hereby incorporated by reference into this application.
This invention relates to an asynchronous transfer mode system for, and method of, transferring cells using a control queue in a control memory on one side of a system bus and a status queue in a host memory on the other side of the system bus.
BACKGROUND OF THE INVENTIONTelephone systems in the United States provide central offices for receiving signals from calling telephones within a particular radius such as one (1) to two (2) miles from the central office and for transmitting telephone signals to such telephones. The telephone signals from a calling telephone are then transmitted through long distances from such central office. The telephone signals then pass to a receiving telephone through a central office within a radius of one (1) mile to two (2) miles from such central office.
The telephone signals are transmitted long distances between central offices through optical fibers which have replaced other media previously provided for such purposes. The optical fibers have certain distinctive advantages over the lines previously provided. They allow a significantly increased number of signals from different telephones to be transmitted at the same time through the optical fibers. They pass the digitally-encoded signals with a higher accuracy than other media.
Various systems have been adopted to carry digitally-encoded signals for telephone, video, and data services. One of such systems now being adopted is designated as asynchronous transfer mode (ATM). This system is advantageous because it recognizes that generally signals travel in only one direction at any one time between a calling subscriber and a receiving subscriber. The system preserves bandwidth in the other direction so that a maximum number of different messages can be transmitted in such direction.
In the prior art, when passing data cells from a control memory at a first station to a host through a system bus and then from the host to a recipient, the host remained on the system bug during all of such transfer. This was disadvantageous because the recipient received information from the host only intermittently. During the time that the recipient did not receive data cells from the host, the system bus was still connected to the host so that the system bus could not be used to transfer data cells for other purposes. As a practical matter, the system bus was tied to the host about seventy percent (70%) of the time. This allowed the system bus relatively little time to perform other functions.
BRIEF DESCRIPTION OF THE INVENTIONIn one embodiment of the invention, a status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the SAR periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.
In the drawings:
The signals in the lines 16 and 18 pass to the access multiplex 20. The respective digitally-encoded transmit signals are segmented into fixed-length cell payloads and a cell header is added to each cell payload to form a cell. Similarly, received cells are reassembled into the respective receive cells. The headers of the cells are generated in the access multiplex to provide a virtual channel indication and/or a virtual path indication. The header indicates the path which is being followed to pass the cells to a central office 22. The central office 22 may modify the header again in the cells to identify the path through which the cells are subsequently being transferred. The cells may then be transferred either to a television access 24 or to a telephone access 26 at receiving stations generally indicated at 28 in
The header in each cell is introduced from the reassembly state machine 40 to a control memory 38 which processes the header to provide addresses that indicate where the cell payloads are to be stored in the host memory 32. The addresses are then applied through the reassembly state machine 40 to the reassembly direct memory access (DMA) stage 36 to direct the payload from the FIFO 34 through a host interface 42 to a host bus 44. The cells are then transferred in the host memory 32 to the addresses indicated by the control memory 38.
Cells may also be transferred to a transmit cell interface through a line 45 by the sub-system 29 shown in
Each of the virtual channel connections contains a table 75 which provides certain information including the address of a region of the host memory 38, the length of the region in the host memory and the protocol information for the virtual channel connection VCC.
The cell from the line 30 in
As the successive cell payloads for the VCC 2 table 73 are reassembled in the region, a check is made in each reassembly to determine if the end of the region in the VCC 2 channel connection has been reached. This is indicated at 84 in
If the end of the region in the VCC 2 table in the control memory 38 has been reached, a “Yes” indication is provided from the block 84. This causes a block 88 to be activated in
Entry 2 in the Free Region Queue contains a new region address in the host memory 38 and the length of such region. This information is transferred to the table 75 in place of the information previously recorded in the table. The blocks 78, 80, 82, 84, 86 and 88 are now operated as discussed above to transfer the payloads in the cells on the line 30 to the regions in the host memory 32. At the end of this region, entry 3 in the Free Region Queue may be selected to provide a new region address in the host memory 32 and the length of such region if the payload has not been completely recorded in the host memory 32. The steps described above are repeated in this manner until all of the payload has been recorded in the host memory 32.
If a cell has been scheduled for the particular time slot, the block 100 in
The header value and the protocol information in the VCC 2 block are read from the control memory 38 as indicated at 108 and 109 respectively in
If the end of the host region in the VCC 2 virtual channel connection has not been reached as indicated at 120 in
When the end of the region in the virtual channel connection VCC 2 has been reached, the address of the next region in the host memory 38 and the length of this region are read as indicated at 124. This next region is indicated as “next” in the table 106 and is indicated in additional detail by a table 128 in
A status queue 132 is shown on the host side of the PCI bus 130. The status queue 132 may be considered to be included in the host memory 32 in
The status queues 132 in
The status queue 132 and the control queues 131 are disposed in a control plane. The buffers 134a, 134b and 134c and the buffer descriptors 136a, 136b and 136c are disposed in a data plane. The separation between the control plane and the data plane is indicated by a broken line 138 in
When data cells are to be transferred from the host memory 32 to the line 45 in
During the transfer described in the previous paragraph, the control queue 131 in
As will be appreciated from the above discussion, the control queue 131 in
In response to the control information described in the previous paragraph, the buffer descriptors 136a, 136b and 136c provide for the transfer of the cell payloads in the buffers 140a, 140b and 140c across the PCI bus 130 to the SAR 29 for passage to the line 45 in
As will be seen, buffers (134a, 134b and 134c) are provided only on the host side of the PCI bus 130. However, buffer descriptors (136a, 136b and 136c and 140a, 140b and 140c) are provided on both sides of the PCI bus 130. The buffer descriptors 146a, 140b and 140c are provided on the SAR side of the PCI bus 130 so that the SAR 29 will not have to read across the PCI bus 130. The SAR 29 is able to read the buffer descriptors 140a, 140b and 140c on the SAR side of the PCI bus 130 and provide the indications to the host that all of the cell payload in the buffers 134a, 134b and 134c has been transferred from the host to the line 45.
A read pointer 148 is provided in the host to the status queue 132. This pointer is designated as “READ”. This pointer indicates the address in the status queue 132 in
As indicated by the pointer 162, the host writes periodically across the PCI bus 130 to the SAR 29 the address where information is being read by the host out of the status queue 132. This writing occurs only periodically to minimize the amount of time that the PCI bus 130 is tied up in the writing of such address from the host to the SAR 29. A pointer 164 is also provided from the SAR across the PCI bus 130 to the status queue 132. This pointer is designated as “WRITE”. It provides an indication from the SAR of the address in the status queue 132 in
In
In
The word “Circular” is used in
The functions shown in
In the next entry, the current position of the host in the control queue 131 in the control memory 38 is incremented by an integer. This is indicated at 204 in
If the current address of the host in the control queue 131 in the control memory 38 is not the same as the last known address in the control queue as seen by the SAR, an indication is provided at 210. The host then writes across the PCI bus 130 into the control queue 131 in the control memory 38 with valid=1. This is indicated at 212 in
As a first step as indicated at 240 in
Valid is a bit in the control queue 131 in the control memory 38. A test is made as at 246 in
The control information in the control queue 131 in the control memory 38 tells the SAR sub-system 29 the addresses of the buffers 134a, 134b and 134c. After the SAR has processed this information, the VLD (valid) entry in the control queue becomes 0. This is indicated at 256 in
In one sense, it is desirable that the fixed number (e.g. 5) of cycles should be large to minimize the amount of time that the PCI bus is tied up by the transfer of information across the PCI bus 130 from the host to the SAR sub-system 29. On the other hand, increasing the fixed number of cycles is disadvantageous because it decreases the accuracy of the information in the period of time between the successive number of processing cycles until the next fixed number (e.g. 5) of processing cycles has occurred.
As a first step in the processing cycles shown within the broken block 258 in
When the count of the number of the processing cycles is other than the fixed number (e.g. 5), the count is incremented upon the occurrence of each successive processing cycle. This is indicated at 269 in
As a first step in
If the status queue 132 in the host is not full, the SAR sub-system 29 indicates the last known position in the status queue as seen by such SAR sub-system. This is indicated by the READ_UD pointer 162 in
The WRITE pointer 164 (
A binary 1 is written into the status queue 132 as indicated at 350 in
As a first step, the host provides a poll interval as indicated at 360 in
As indicated at 364, the host then reads the next entry that the SAR sub-system 29 writes to the host. The host then determines whether valid=1 as indicated at 366 in
A determination is then made, as indicated at 374, whether a fixed number (e.g. 5) of processing cycles has occurred. The determination of the fixed number (e.g. 5) of the processing cycles is made in blocks within a rectangle 375 with broken lines. If the answer is yes as indicated at 376 in
If the count of the number of processing cycles is not equal to the fixed number (e.g. 5), an indication is provided on a line 384 in
Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments which will be apparent to persons of ordinary skill in the art. The invention is, therefore, to be limited only as indicated by the scope of the appended claims.
Claims
1. A method for operating a system comprising an Asynchronous Transfer Mode Segmentation and Re-assembly (SAR) connected to a host, the method comprising:
- writing from the SAR to the host to indicate where the SAR is reading from a SAR queue;
- writing from the host to the SAR to indicate where the host is reading from the host queue;
- transferring information between the host queue and the SAR queue; and
- transferring a first cell payload between the host and the SAR in response to transferring the information.
2. The method of claim 1 further comprising:
- writing from the SAR to the host to indicate where the SAR is writing to the host queue; and
- writing from the host to the SAR to indicate where the host is writing to the SAR queue.
3. The method of claim 2 further comprising:
- controlling the SAR queue to indicate if the information in the SAR queue has been processed; and
- controlling the host queue to indicate if the information in the host queue has been processed.
4. The method of claim 3 wherein:
- transferring the information comprises writing a first pointer from the host to the SAR queue; and
- transferring the first cell payload comprises reading a first cell payload from a first buffer in the host in response to the first pointer in the SAR queue.
5. The method of claim 4 wherein reading the first cell payload from the host in response to the first pointer in the SAR queue comprises activating a first SAR buffer descriptor in response to the first pointer in the SAR queue and reading the first cell payload from the first buffer in the host in response to activating the first SAR buffer descriptor.
6. The method of claim 5 wherein the first SAR buffer descriptor is associated with the first buffer in the host and the first pointer indicates the first SAR buffer descriptor.
7. The method of claim 6 further comprising:
- activating a second SAR buffer descriptor in response to reading the first cell payload from the first buffer in the host; and
- reading a second cell payload from a second buffer in the host to the SAR in response to activating the second SAR buffer descriptor.
8. The method of claim 4 further comprising writing a second pointer from the SAR to the host queue in response to transferring the first cell payload to the SAR to indicate that transfer of the first cell payload is complete.
9. The method of claim 8 wherein the second pointer indicates a first host buffer descriptor that is associated with the first buffer.
10. The method of claim 9 further comprising mirroring the first host buffer descriptor and the first SAR buffer descriptor.
11. The method of claim 3 wherein:
- transferring the information comprises writing a first pointer from the host to the SAR queue; and
- transferring the first cell payload comprises writing a first cell payload from the SAR to a first buffer in the host in response to the first pointer in the SAR queue.
12. The method of claim 11 wherein writing the first cell payload from the SAR to the host in response to the first pointer in the SAR queue comprises activating a first host buffer descriptor in response to the first pointer in the SAR queue and writing the first cell payload from SAR to the first buffer in the host in response to activating the first host buffer descriptor.
13. The method of claim 12 wherein the first host buffer descriptor is associated with the first buffer in the host and the first pointer indicates the first host buffer descriptor.
14. The method of claim 13 further comprising:
- activating a second host buffer descriptor in response to writing the first cell payload from the SAR to the first buffer in the host; and
- writing a second cell payload from the SAR to a second buffer in the host in response to activating the second host buffer descriptor.
15. The method of claim 11 further comprising writing a second pointer from the SAR to the host queue in response to transferring the first cell payload to the host to indicate that transfer of the first cell payload is complete.
16. The method of claim 15 wherein the second pointer indicates the first host buffer descriptor that is associated with the first buffer in the host.
17. An Asynchronous Transfer Mode (ATM) system comprising:
- a Segmentation and Re-assembly (SAR) queue configured to store information from a host wherein the host is configured to write to the SAR queue to indicate where the host is reading from a host queue; and
- a SAR circuit configured to write to the host to indicate where the SAR circuit is reading from the SAR queue and to transfer a first cell payload between the host and the SAR circuit in response to the information in the SAR queue.
18. The ATM system of claim 17 wherein the SAR circuit is configured to write to the host to indicate where the SAR is writing to a host queue.
19. The ATM system of claim 18 wherein the SAR queue is configured to indicate if the information in the SAR queue has been processed.
20. The ATM system of claim 19 wherein the information comprises a first pointer and the SAR circuit is configured to read a first cell payload from a first buffer in the host in response to the first pointer in the SAR queue.
21. The ATM system of claim 20 wherein the SAR circuit includes a first SAR buffer descriptor and the SAR circuit is configured to activate the first SAR buffer descriptor in response to the first pointer in the SAR queue and to read the first cell payload from the first buffer in the host in response to activating the first SAR buffer descriptor.
22. The ATM system of claim 21 wherein the first SAR buffer descriptor is associated with the first buffer in the host and the first pointer indicates the first SAR buffer descriptor.
23. The ATM system of claim 22 wherein the SAR circuit includes a second SAR buffer descriptor and the SAR circuit is configured to activate the second SAR buffer descriptor in response to reading the first cell payload from the first buffer in the host and to read a second cell payload from a second buffer in the host in response to activating the second SAR buffer descriptor.
24. The ATM system of claim 20 wherein the SAR circuit is configured to write a second pointer to the host queue in response to reading the first cell payload to indicate that transfer of the first cell payload is complete.
25. The ATM system of claim 24 wherein the second pointer indicates a first host buffer descriptor that is associated with the first buffer.
26. The ATM system of claim 19 wherein the information is a first pointer and the SAR circuit is configured to write a first cell payload a first buffer in the host in response to the first pointer in the SAR queue.
27. The ATM system of claim 26 wherein the host includes a first host buffer descriptor and the SAR circuit is configured to activate the first host buffer descriptor in response to the first pointer in the SAR queue and to write the first cell payload to the first buffer in the host in response to activating the first host buffer descriptor.
28. The ATM system of claim 27 wherein the first host buffer descriptor is associated with the first buffer in the host and the first pointer indicates the first host buffer descriptor.
29. The ATM system of claim 28 wherein the SAR circuit is configured to write a second pointer from the SAR to the host queue in response to transferring the first cell payload to the host to indicate that transfer of the first cell payload is complete.
30. The ATM system of claim 29 wherein the second pointer indicates the first host buffer descriptor that is associated with the first buffer in the host.
31. The ATM system of claim 19 further comprising the host wherein the host is configured to write to the SAR to indicate where the host is reading from a host queue and where the host is writing to the SAR queue.
32. The ATM system of claim 31 wherein the host is configured to indicate if the information in the host queue has been processed.
33. The ATM system of claim 32 wherein the SAR circuit includes a first SAR buffer descriptor and the host includes a first host buffer descriptor and the SAR circuit and host are configured to mirror the first host buffer descriptor and the first SAR buffer descriptor.
5796735 | August 18, 1998 | Miller et al. |
0 551 191 | July 1993 | EP |
WO 96/08896 | March 1996 | WO |
- Tomimitsu, Yasuharu, “An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput,” IEICE Transactions on Electronics, Dec. 1995, No. 12 Tokyo, JP.
Type: Grant
Filed: Nov 4, 1999
Date of Patent: Mar 7, 2006
Assignee: Mindspeed Technologies, Inc. (Newport Beach, CA)
Inventors: Bradford C. Lincoln (Boulder, CO), David R. Meyer (Lakewood, CO)
Primary Examiner: Chi Pham
Assistant Examiner: Alexander O. Boakye
Attorney: Keith Kind
Application Number: 09/433,850
International Classification: H04L 12/28 (20060101);