Abstract: A method for realizing alignment marks on a semiconductor device employs a thicker dielectric layer than in the prior art. The method is used during a manufacturing process including at least a Chemical Mechanical Polishing process step, and includes forming alignment marks on a portion of a semiconductor substrate; masking the marks portion during a further deposition step of a first conductive layer covered by a first dielectric layer; depositing a first conformal metal layer over the first dielectric layer and over the marks portion; depositing a second dielectric layer over the first metal layer; and performing a CMP process step to planarize the second dielectric layer; wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers the alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize the marks portion.

Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well as allowing the heat dissipation to be distributed over a number of operational amplifiers, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power is dissipated.

Abstract: A comparator of a first digital value of n bits having CMOS voltage levels with a second digital value of n bits having ECL, or CML voltage levels, including a decoder in CMOS technology provided to provide 2n CMOS signals, each of which corresponds to a different product of n bits, each of the n bits being a respective bit of the first digital value or its complement; 2n AND gates in ECL or CML technology respectively associated with the 2n CMOS signals, connected to implement an OR function of 2n ECL or CML signals, each of which corresponds to a different product of n bits taken from among the bits of the second value or their complements, according to the same choice as for the product of n bits of the respective CMOS signal; and means for deactivating the AND gates associated with the CMOS signals to 0.

Abstract: On a substrate of semiconductor material, a sacrificial region is formed and an epitaxial layer is grown; a stress release trench is formed, surrounding an area of the epitaxial layer, where an integrated electromechanical microstructure is to be formed; the wafer is then heat treated, to release residual stress. Subsequently, the stress release trench is filled with a sealing region of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region, a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

Abstract: A process formes a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer depositing and partly defining a first polysilicon layer forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor depositing a second polysilicon layer selectively etching away the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor and selectively etching away the interpoly dielectric layer and the first polysilicon layer at the cell.

Abstract: A method for identifying fingerprints includes the steps of acquiring a primary image and a secondary image; determining notable points in the primary image; comparing with one another the primary image and the secondary image in order to identify the correspondences between the primary image and the secondary image; and validating the possible correspondences. The comparison between the primary image and the secondary image is based on comparison of the regions which surround the notable points on the primary image, with all the points of the secondary image, through a flash cell array, such as to obtain lists of points in the secondary image which are probably associated with the notable points.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.