Abstract: A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

Abstract: The invention provides an apparatus and a method for converting instructions of a code A to instructions of a code B. Said conversion is performed by obtaining rearrangement information, which corresponds to the instruction that is to be converted, from a table. Said rearrangement information is then used to rearrange the instruction elements of the initial instruction, in order to generate instructions of code B, which functionally corresponds to said initial instruction. Said rearrangement can be performed by multiplexing means, which use said instruction elements of the initial code A instruction as input, and which select one of said instruction elements, or the content of another register, and forward this selected data to the instruction that is to be generated. Said rearrangement information is directly used to control the selection performed by said multiplexers.

Abstract: The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.

Abstract: A method and apparatus for configuring a centralized arbitration scheme for a commonly accessed communication bus using arbiter devices with arbitration control circuitry included therein. The arbiter devices, each of which is associated with a separate bus master device, include arbitration control circuitry and are coupled to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same arbiter device connections to the arbitration control bus provide signals which are decoded via arbitration configuration circuitry on each device to provide a configuration status indicating whether other devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the required arbitration.

Abstract: A method and apparatus for passing messages between nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings between which messages are to pass may be provided with a token indicative of this condition. The token may further be associated with message parameters defining the passage of the message and operations to be performed thereon, between the two nodes represented by the intersecting row and column headings. Successive versions of the two dimensional array may be provided to form a three dimensional array for passing messages between nodes over the network via successive communication patterns defined by the successive versions of the two dimensional array.

Abstract: Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses.

Abstract: Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol field (called herein a PLT, program lock token, field), a lock field H, and a wait field W which is used to chain plural CLEs currently having the same blocking symbol. When the lock field H is set to a lock held state, it indicates the associated processor has exclusive rights to access a data resource unit associated with the blocking symbol in the CLE entry. When the wait field in a lock entry contains a pointer to another lock entry and the H field in the lock entry indicates a not held state, the associated processor is waiting for the resource and cannot further execute its PLO instance until it later gets set to the lock state, which is done by the processor of the prior CLE in the chain when it completes execution of its PLO instance. Each PLO instruction also has operand fields, and a function code (FC).

Abstract: PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol.

Abstract: An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical busses each including two or more physical busses for coupling multiple processors to a memory unit. Each logical bus is coupled to a bus switching unit which in turn couples all of the processors in the multiprocessor system to a memory unit over the physical busses comprising the logical bus. The system further manages near end signal reception problems caused by multiple processors electrically interconnected over such a bus system.

Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.

Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.

Abstract: A method and apparatus for performing operations at nodes in a distributed network of interconnected nodes wherein a two dimensional array is arranged with each of the nodes represented by a single row heading and a single column heading. The intersections of row and column headings at which operations are to be performed may be provided with a token indicative of this condition. The token may further be associated with operation parameters defining the performance of the operations at the two nodes represented by the intersecting row and column headings.

Abstract: A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.

Abstract: A method and apparatus for implementing a user programmable interrupt mask and timeout count. A master mask latch receives non-privileged instructions which alternatively cause the latch to disable and enable interrupt requests for the processor. The non-privileged disable interrupts instruction additionally causes the initiation of a timeout counter for defining the duration of an interval for which interrupt requests may be disabled. The non-privileged enable interrupts instruction additionally terminates the count of the timeout counter. If the timeout counter is not halted within the defined interval, a system error interrupt is generated, interrupts are re-enabled and the counter is halted. In a further embodiment, the disable interrupts instruction may be incorporated into a fetch and hold instruction and the enable interrupts instruction may be incorporated into a store and release instruction to facilitate atomic read, modify, write operations.

Abstract: Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system.

Abstract: A method for improved use of bandwidth on a bus. A bus, such as a processor bus between a processor and an L2 cache, is established having two states: a first state in which one half of the bus allows transmission in one direction and the other half allows transmission in the opposite direction; and a second state in which the entire bus bandwidth comprising both bus halves allow transmission in one direction. To achieve this bus design, means are provided for selectively switching at least one of the bus halves' transmission directions.

Abstract: The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only control store 5 for storage of microinstructions. The random access control store includes a flag microinstruction (REPmark1) for indicating that another microinstruction (add W, 2, W1), stored in the read only control store 5, is faulty. The control stores are coupled to a multiplexer 8 and are adapted to output the microinstructions in parallel to the multiplexer 8 which is in turn coupled to the processor and which selectively provides output from either the random access control store or the read only control store to the processor 1. The apparatus also includes a decoder coupled to the random access control store for observing the microinstructions output therefrom. The decoder is further coupled to inhibiting logic in the processor and outputs a signal if the flag microinstruction is output from the random access control store.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system are disclosed. A memory controller may be connected to a memory bank inserted into a memory bank insertion area, via an interconnect line such as row address strobe (RAS) signal line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks, type detection operations may be performed on the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.

Abstract: A method and apparatus for establishing deadlock free routing in a bi-directional, multi-stage, inter-connected, cross-point based packet switch, particularly, though not exclusively employed within a high speed packet network of a massively parallel processing system. Specifically, a group of sets of restricted routes traversing a source, intermediate and destination switch chip are determined by establishing a number of route restrictions from each source switch in the network and determining a number of routes restricted between each source-destination pair of switch chips therein, such that the standard deviation for the number of routes left unrestricted between all source-destination pairs of switch chips for the packet network is minimized.