Abstract: A power supply control circuit for conditioning an electronic circuit's input voltage at ground or at the operation voltage of an external power supply so as to permit the electronic circuit to receive a supply voltage at ground potential until the power supply transitions above a threshold voltage level and thereafter to provide operation level voltage of the power supply to the electronic circuit. The circuit comprises a transconducting means having its high current node coupled to an external power supply, its controlling node coupled to a voltage reference means. The transconducting means has its controlled high current node coupled through a power input node to the power input for the electronic circuit to condition the voltage received thereby. The power input node is in turn coupled through a pull down means to ground potential.

Abstract: A method and apparatus for detecting a supply voltage loss from a PCMCIA power source across a PCMCIA interface. The voltage loss may correspond for example, to the removal of a PCMCIA card from a PCMCIA host computer system. The invention provides for detection and reporting of said supply voltage loss to another apparatus capable of operating at lower voltage levels than that supplied by the PCMCIA power source. The rate of supply voltage loss is controlled, and an indication of the loss is provided to the other apparatus so as to allow sufficient time for the apparatus to take appropriate actions in response to the loss of supply voltage.

Abstract: For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.

Abstract: The invention relates to an apparatus for establishing an electrical and/or optic connection of a first and a second component with a third component with connection means 14, 15 for electrical and/or optic connection of the first and second component with each other, whereby the connection means 14, 15 allow mechanical free-play between the first and second component, with a connection link 13, 16 each for the first and the second component for electrical and/or optic connection of the first and the second with a third component, and with an apparatus 31, 32, 33, 34 for limitation of the mechanical free-play between the first and the second component.

Abstract: A method and apparatus for establishing deadlock free routing in a bi-directional, multi-stage, inter-connected, cross-point based packet switch, particularly, though not exclusively employed within a high speed packet network of a massively parallel processing system. Specifically, a group of sets of restricted routes traversing a source, intermediate and destination switch chip are determined by establishing a number of route restrictions from each source switch in the network and determining a number of routes restricted between each source-destination pair of switch chips therein, such that the standard deviation for the number of routes left unrestricted between all source-destination pairs of switch chips for the packet network is minimized.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner.

Abstract: A method for testing electronic assemblies having an electronic component affixed via solder or other such connections to a printed circuit board. The method includes combining, in order, three sequential stress test steps, into a single stress test for screening defects in the electronic assemblies. In particular, the test combines a thermal cycling stress test followed by a electrical burn-in stress test coupled with functional monitoring of the assembly, followed by a random vibration stress test coupled with functional monitoring of the assembly, each test is imposed with defined parameters upon the electronic assembly. The combination, order, and parameters of the sequential stress test steps provide a single test for electrical assemblies which substantially screens all such assemblies having systematic or random defects while imparting minimal reduction in useful life to the defect-free assemblies by virtue of the testing, thereby resulting in a high reliability product.

Abstract: Provides data and program integrity in a computer system by guarding against malicious program operation when using the Branch In Subspace Group instruction (BSG) of the S/390 computer architecture. System integrity is ensured by providing a controlled target space (a base space) and branch address during a BSG transfer of control (branch) from a subspace, and a different PSW key mask (PKM) for the base space than for subspaces. More specifically, (1) the PKM is reduced and a new PSW access key is set during a BSG branch from the base space to a subspace, (2) the original PKM and access key and also a return address are saved in a secure data area during the same branch, and (3), during a branch from a subspace, the original PKM and access key are restored, and the branch is made to the return address (the controlled branch address) in the base space.

Abstract: A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generator coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generation device coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level.

Abstract: A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage.

Abstract: Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages.

Abstract: A cache memory is provided which adjusts its response to addresses in accordance with the number of identical cache memory cards installed in the motherboard. Upon its installation in the motherboard a card is informed of its status as a master or a slave. As long as a slave is not installed the master responds to processor accesses over the entire address range of the computer. When a slave is installed a signal is sent to the master. Circuitry on the memory cards restricts the master response to half the address range. The slave being informed of its status restricts its response to the other half of the address range.

Abstract: It is an object of the present invention to restrict EMI radiation at a specific frequency by inserting a delay time that is effective for that frequency. The feature of the present invention is to provide a delay generator that can selectively alter delay times. The delay generator comprises: delay means, which is connected to a plurality of data input lines, and which has a plurality of delay paths for the generation of a plurality of alternative delay times; a register for storing a digital value of pre-determined bit; and selection means for selecting one of the delay paths in consonance with the digital value and for providing the selected delay path for the signal lines.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.

Abstract: The cache controller of a second level cache in an Intel Pentium processor based computer system contains test circuitry that allows reading and writing directly into all tag RAM databit locations. This circuitry responds to a modified External Address Strobe (EADS#) command to invoke the tag test cycle. The EADS# command is normally used in a SNOOP read cycle by the system. In a SNOOP cycle, the main memory controller invokes the EADS# command to request the first level (L.sub.1) and second level (L.sub.2) caches for modified information stored in those caches. In the tag test cycle the EADS# command line is held down twice as long as it would in a normal SNOOP read Cycle. Because of its added length, the SNOOP cycle circuits in the L.sub.2 cache ignore the command on the EADS# command line. However, the tag RAM test circuitry in the L.sub.