Abstract: A paste composition having a high thermal conductivity and a relatively low viscosity is used to provide a thermal conductive connection between an electronic component and a cooling device to increase the heat transfer rate between the component and the device cooling the electronic component. The paste composition comprises a non-aqueous dielectric carrier, thermally conductive filler particles and a specially defined dispersant comprising the self-condensation reaction product of a hydroxy fatty acid, the reaction product having an acid number of about 30-100. A 12-hydroxy stearic acid self condensed reaction product is the preferred dispersant.

Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.

Abstract: The present invention relates generally to a new electrode forming metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: The present invention relates generally to a new metal/ceramic laminate magnet and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area laminate magnet with a significant number of holes, integrated metal plate(s) and electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display and electron beam source and methods of manufacture thereof.

Abstract: The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.

Abstract: A method for preparing a semiconductor material for formation of a silicide layer on selected areas thereupon is disclosed. In an exemplary embodiment of the invention, the method includes removing at least one of a nitride and an oxynitride film from the selected areas, removing metallic particles from the selected areas, removing surface particles from the selected areas, removing organics from the selected areas, and removing an oxide layer from the selected areas.

Abstract: A method for forming a multilevel interconnect structure for an integrated circuit is disclosed. In an exemplary embodiment of the invention, the method includes forming a starting structure upon a substrate, the starting structure having a number of metallic conducting lines contained therein. A disk is bonded to the top of said starting structure, the disk including a plurality of mesh openings contained therein. The mesh openings are then filled with an insulative material, thereby forming a cap upon the startig structure, wherein the cap may structurally support additional interconnect layers subsequently formed thereatop.

Abstract: An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters.

Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Abstract: A system for testing every one of the signal inputs and outputs (I/O) of a fine pitch multi-chip semiconductor module utilizing a selective netlist, through the intermediary of presently available test equipment. More particularly, the system facilitates the testing of fine pitch multi-chip modules utilizing 1.0 mm ceramic column grid array (CCGA) technology in order to facilitate the use of increased system interconnect capabilities. Additionally, there is provided a method of employing a selective netlist in order to test fine pitch multi-chip semiconductor modules; especially such as, but not limited to 1.0 mm pitch ceramic column grid array (CCGA) modules by employing commercially available test equipment.

Abstract: A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Abstract: The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for aligning a projected photolithography mask pattern image with respect to the underlying device layer. The method involves measuring the overlay error between product features in the projected layer and product features in the underlying layer, determining an adjustment factor based on these measurements, and applying this adjustment factor to the overlay error between reference features located in the kerf of the projected layer and reference features in the kerf of the underlying layer. Thus, nonzero offsets or adjustment factors for box-in-box overlay targets are entered into a stepper or scanner tool, in order to minimize within field product overlay errors.

Abstract: A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET). The method forms an insulator layer over a substrate and a doped layer over the insulator layer. Further, the invention patterns a conductor layer over the doped layer. The conductor layer includes gate conductors. The invention implants a second impurity through the conductor layer and into the doped layer. The second impurity is of an opposite type than that of the first type of impurity. Also, the second impurity decreases the effective concentration of the first impurity in the doped layer. The amount of the second type of impurity that penetrates through the conductor layer into the doped layer changes depending upon the length of the gate conductors within the conductor layer.

Abstract: The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

Abstract: A multilayer thin film structure having defined strap repair lines thereon and a method for repairing interconnections in the multilayer thin film structure (MLTF) and/or making engineering changes (EC) are provided. The method comprises determining interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, defining the top surface metallization including a series of orthogonal X conductor lines and Y conductor lines using photoresist and lithography and additive or phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization.

Abstract: This invention provides a method for treating waste water containing organic bases such as tetramethyl ammonium hydroxide and dissolved metals such as Mo, W, Cu and Ni which are generated from mask cleaning and Mo etching processes. The organic base along with Cu and Ni is first removed preferably by passing the effluent through a cation exchange resin followed by passing the cation exchanged effluent through an anion exchange resin to remove the Mo and W metals. The treated waste water meets federal guidelines for dissolved metal contaminant limits for water discharge to water ways. Alternatively, filtered effluent is directly passed through an anion exchange resin to remove Mo and W and the dissolved TMAH and copper and nickel are removed by cation exchange.

Abstract: A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer.

Abstract: The surface metallurgy of a green sheet may be controlled during processing to provide an increased resistance to low strength structural failure of the metal-ceramic interface under an input-output pad structure and increased pin-pull strength of input-output pads on alumina multilayer ceramic substrates. The surface area on a green sheet in the region where an input-output pad is to be screened is roughened in order to increase the contact surface area between the green sheet and the input-output pad. The mechanical interlock between the metal-ceramic interface is strengthened by the increased number of bonding points between the green sheet and the input-output metallurgy and the use of different screening materials.