Abstract: A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A starting bit code defines the location of the start of the bit field to be written and a field length code defines the number of bits that are to be merged and written. The combination of the starting bit code and the field length code define the ending bit control for the bits to be written, and are further utilized to control word boundary crossing into the next sequentially addressed memory word when the bit field to be written cannot be completed in the addressed word.

Abstract: A flexible moulded plastic panel closure is provided with a plurality of latches and retainers to permit the flexible moulded plastic panel to be attached through an aperture in a rigid wall of a chassis of a video display terminal. The flexible moulded plastic panel is provided with a plurality of resilient retaining fingers and tolerance springs for precisely mounting and holding an axial flow electric fan in a predetermined position to provide circulated air cooling for heat producing electronic components mounted inside of said rigid chassis.

Abstract: A printing system incorporates a character generator having circuitry for the generation of proportional width printing. Further circuitry is utilized in conjunction with the foregoing circuitry to operate the system in a tabular mode for the columnar presentation of printed material. Two memories are employed. One memory stores data as to the components of characters which are to be printed, the data being stored in predesignated sets of addresses. Each of these components may be addressed by an address counter preset for counting through the set of addresses of a selected character. A tabbing or print signal is stored in the second memory to serve as position data in the tabbing mode. The second memory is addressed concurrently with a scanning of a print line whereby the stored data corresponds to a position on the print line.

Abstract: A video display terminal (VDT) is provided with a controller having six digital logic lines capable of defining sixty-four different colors. An eight color color display monitor (CDM) having three red, green and blue (RGB) video input lines is connected to a pulse width modulation converter capable of converting the sixty-four digital input conditions on the six low level voltage logic lines to sixty-four different color control conditions on the three video input lines.

Abstract: A relatively short broad band monopole coaxial antenna is provided with a center conductor and an outer radiator. The antenna is mounted above a ground plane and comprises a bare outer radiator portion adjacent the ground plane and a portion remote from the ground plane which is covered with a variable thickness microwave absorbent material. The signal to be transmitted is applied to the base of the monopole antenna adjacent the ground plane. Non-radiated signals propagate up the antenna. The high frequency components are absorbed by the microwave absorbing material. A tip matching network and a base matching network are coupled between the outer conductor and the ground plane for attenuating and matching the low frequency components of the non-radiated signals. The resulting monopole coaxial antenna has no undesirable reflections and has the appearance of infinite effective length antenna.

Abstract: An accurate radio frequency ranging system is provided for measuring the time required for a signal to be transmitted from a ground station to a remote station and to be returned to the ground station. The ground station is provided with a master reference clock that is employed to drive a first pseudonoise generator. The ranging system in the ground station is started by a unique and predetermined start epoch signal produced by the first pseudonoise generator. The first pseudonoise generated signals are transmitted to the remote station where they are tracked and sensed. When the original start epoch signal is sensed at the remote station, it is employed as a trigger or read signal to initiate the generation of a stop epoch signal. The stop epoch signal is retransmitted to the ground station and stored in a register where it is compared with pseudonoise generated signals being retransmitted from the remote station to the ground station.

Abstract: A programmable force assembler for robots includes a bi-directionally actuatable slide member. A microprocessor is programmable for controlling insertion force independent of the distance moved by the slide member. A position indicator transmits slide member distance signals and velocity information to the microprocessor. A pressure transducer is connected to the bi-directional actuator and is coupled to send signals to the microprocessor. A supply valve is connected to the bi-directional actuator and is coupled for receiving signals from the microprocessor in response to the pressure transducer signals.

Abstract: A superconductive Josephson junction high density memory array is provided. Each memory cell in the array comprises a two branch superconducting interferometer storage loop which has only a single Josephson junction device in one of the branches. The Josephson junction devices are mounted on a substrate having a patterned ground plane. The ground plane pattern is provided with holes or apertures which surround the Josephson junction devices so that the control current of the control lines couple with the tunnel junctions of the Josephson junction devices but not with the ground plane. This structural arrangement provides a threshold characteristic for the single Josephson junction device which is symmetrical to the gate current, thus, may be easily switched to two current states indicative of two logic states.

Abstract: A drilling monitor employs laser optics and an associated signal processing device to provide intelligent control capable of making the optimum decision to maintain hole quality and maximize drill life during the drilling of via holes in a circuit board. Twist angle, bending and temperature of the drill are monitored and the drill motor and/or the board is controlled accordingly in response to present data being compared to preprogrammed acceptable standardized data.

Abstract: A superconducting quantum interference device (SQUID) is direct current biased through physical connections asymmetric to, and preferably maximally asymmetric to, the two Josephson junctions. The asymmetric SQUID so created is, responsively to such physical asymmetry, biased for operation in the linear region of the input magnetic flux/output (voltage or current) device response curve. A resistance of specified value is connected in parallel, or shunt, to the parasitic bridge capacitance of the asymmetric SQUID in order to minimize hysteresis. Two asymmetric SQUIDS of opposite asymmetry are serially connected as a push-pull linear amplifier stage which exhibits zero output (voltage or current) at zero input magnetic flux, and which is specifiable in parameters of construction so as to exhibit optimum linearity of response about such point.

Abstract: There is shown and described a relatively simple electronic circuit using few discrete components which is used to replace the filter and delay line differentiator in existing circuits. The new circuit provides a simultaneous output of even and odd signals which have the same transfer function except for the derivative operation. The circuit is especially useful in read and write channels of a disk drive apparatus.

Abstract: A method of and apparatus for encoding computer program instructions and data greatly reduces the total storage requirements. Upon compiling each computer program segment, statistics are generated regarding the frequency of use of each unique program operator and each unique program operand. The operators and operands are encoded using the information theoretic encoding technique. A conversion table is also prepared which enables the object computer to translate the encoded operands and operators during that time when the computer program segment is being executed. Apparatus within the object computer decodes the encoded operands and operators using the conversion tables enabling execution of the computer program segment.

Abstract: Apparatus and method for encoding binary data in a ternary format including ternary 0, ternary 1 and ternary 2 code symbols. In a preferred embodiment of the invention utilized for magnetic data storage, a ternary 0 is represented by the absence of signal change, a ternary 1 is represented by a single transition and a ternary 2 is represented by a pulse or pair of closely spaced transitions. Further features of the invention provide for merging ternary code symbols so as to prevent the spacing between adjacent symbols from becoming so small as to create undesirable crowding, and inserting and shifting symbols to prevent the spacing between adjacent symbols from becoming so great as to adversely affect recovery of the encoded data.

Abstract: A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, temperature, sensor via a second diode (system ground is a return). A multiplicity, nominally 16, of such single wire connected sensor pairs are selectable in accordance with an externally (microprocessor) furnished address. During a first time period, an externally (microprocessor) selected interrogation of temperature causes a first, positive, voltage bias to be applied to the selected sensor pair resulting in a current linear with temperature (over the range of 0.degree. C. to 100.degree. C.) in the second sensor. This current is transformed to voltage, offset by 273.degree. Kelvin, amplified, and converted to a digital value for issuance to an external (microprocessor) requestor.

Abstract: A high speed data base search system which contains a general purpose computer coupled to a special purpose processor called the High Speed Search Function or HSSF. The HSSF may be external to the computer having a standard Input/Output communication path. An alternative approach places the HSSF internal to the computer providing communication via an internal bus. The HSSF is identical in either configuration except for the interface logic. The HSSF is programmable by the computer to perform complex searches on variable size data bases. The internal memory of the HSSF is loaded with the data base to be searched. Registers within the HSSF are loaded with reference words which define the search bounds. The field format register of the HSSF is loaded with a definition of the data base. The field comparison register is loaded to define the field-by-field search criteria. The Boolean Expression loaded into the HSSF defines which compare results are to be considered a hit.

Abstract: A method and apparatus for pseudorandomly decrementing the intensity of data that is displayed on a raster scan display screen. The apparatus essentially comprises means for selecting and partially decrementing data from an image memory and means for controlling the rate at which the partially decremented data is written back into the image memory so that an apparently uniform phosphor decay rate is observed by a viewer.

Abstract: A cooling system monitoring assembly incorporating a heat generating element for simulating heat generation of components in the system, together with heat sensing element responsive to the heat generating element for providing temperature signals when the temperature of the heat generating element is sensed to have exceeded a predetermined threshold is described, thereby indicating the level of temperature fault. A support assembly is described for supporting the heat generating element in the heat transfer relationship to the monitored cooling system, while supporting the heat sensing element. A system for monitoring a plurality of subassemblies associated with the monitored cooling system and identifying the location of detected temperature fault condition is also described.

Abstract: A Drill Bit detector for use with numerically controlled drilling machine capable of sensing missing or broken Drill Bits in the range of 1 mil to 30 mils in diameter, or larger, is described. An infrared emitting diode is driven at a predetermined frequency with the pulsed light being directed through fiber optic cable directed at a portion of the Drill Bit to be detected. A change of light intensity occurring when a Drill Bit is missing is detected and the pulsed light detected converted to a pulsating electrical signal at the input frequency of the pulse light source. A frequency responsive circuit converts the pulsating electrical circuit to a digital signal indicative of the absence of the sensed Drill Bit. A timer determines whether or not the sensed digital signal occurs for a predetermined threshold time period, and causes it to be ignored as spurious if less than the predetermined time interval, or causes the drilling machine operation to be halted if occurring longer than the threshold time period.

Abstract: A Josephson junction latch circuit is provided which has an AND gate having plural inputs and a single output. The output of the single AND gate is directly coupled to a Josephson junction flux storage loop capable of storing flux indicative of the output of the AND gate. A Josephson junction sense line is provided capable of sensing the flux condition of the flux storage loop. The sense line is directly coupled to amplifying gates which produce amplified true and complement quantities whenever the sense line is actuated.

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.