Abstract: A dehumidifier for a head-disk assembly in a disk drive unit. The dehumidifier includes a housing which is ported to define an air passage therethrough. Within the passage is a Peltier effect device that has a cold surface exposed to air flowing within the passage and a hot surface connected to a heat radiator. Water vapor carried in air that contacts the cold surface condenses; there is sump below the cold surface to contain water that condenses. The housing is installed so that air flow through the passage is induced by convection.

Abstract: The reduction of electromagnetic interference radiation from electrical component housings is enhanced due to an electrically conductive adapter rings each connected to associated electrically conductive cable shields. The rings and cables are engaged and retained by an electrically conductive bar attached to the housing and adapted to receive the rings, and thereby discharge electromagnetic signals to the housing ground potential.

Abstract: A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET. A second feedback loop created guard circuits on the cases of the input FET and the drain circuit regulator transistor, thereby mitigating junction to external circuitry capacitances. A third feedback loop modifies essentially constant current flow in the source circuit of the input FET in order to compensate for capacitance within that circuit. When utilized in compact form for microprobing of low voltage nanosecond rise time signals, the amplifier demonstrates an effective input capacitance of less than 0.5 picofarads.

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N.

Abstract: An improved high speed gallium arsenide (GaAs) to emitter coupled logic (ECL) voltage level converter is provided which consumes less power and also provides an improved speed-power product performance characteristic. The converter includes a three branch output circuit which emulates the operation of an ECL output driver. The emulator circuit causes faster switching by compensating for parasitic resistances and capacitance and is also provided with a gate discharge network which reduces switching time of the ECL output emulator.

Abstract: During the preparation of a Josephson junction device, one of the steps for making a base electrode is to deposit a superconducting material on a substrate and to anneal the deposited material to make it a continuous homogeneous polycrystalline grain-like electrode material. Ordinarily, the base electrode and the counter electrode materials are deposited in a vacuum system at a vacuum pressure which is below one.times.10.sup.-6 torr to remove all contaminants such as oxygen, oxides of carbon and water vapor. It has been discovered that depositing conventional superconducting base electrode and counter electrode materials in the presence of an inert gas at much high vacuum pressures around 20.times.10-3 torr produce a superior lead-gold superconductive electrode which is substantially immune to thermal cycling.

Abstract: Apparatus is disclosed for stacking a continuous paper form having uniformly positioned folds or seams as it exits from a device such as a printer. It utilizes a pair of curved surfaces over which an air flow is alternately directed to alternately create an air film over each of the curved surfaces. This air film attracts the paper in such a manner that the continuous paper form is refolded in a bin or stacker in its original configuration.

Abstract: A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which effectively reduces the resistance of the transistor device and permits the area of the device to be reduced by more than one order of magnitude while maintaining high current and power levels.

Abstract: There is shown and described a high speed bus architecture which uses a common control bus and permits high speed data transfer between a plurality of active and/or passive users while reducing the system overhead structure which was previously required.

Abstract: Ink jet printers include orifices which may become clogged or otherwise inoperative. This can cause printing defects which may go undetected for a substantial period because these printers usually operate unattended. An optical detector is provided for testing the operability of each ink jet orifice prior to the beginning of printing either a print cycle or a page. Ink is deposited on a member which moves the deposit through an optical path for detection. Absence of a deposit signals a malfunction.

Abstract: Direct current inrush upon connection of a capacitive load to a d.c. voltage is limited through an intermediary circuit. Within such circuit the inrush current is sensed by a series resistance and such sensing is utilized via a feedback loop, to control a series current regulating transistor to be cyclically conducting or non-conducting of a first direct current path. A second direct current path through freewheeling diodes flows current to the load only when such series current regulating transistor is non-conducting of such first path current. After fully charging the capacitive load, howsoever slowly as desired, the first current path conducts with low power dissipation while the second current path is non-conducting. The circuit is further controlled to be correctly operative for control of inrush current during the turn-on, or disruption of, fundamental power to such circuit.

Abstract: An oscillating coolant pump includes a pair of opposed bellows mounted to reciprocate in a housing for moving a volume of fluid through a heat exchanger and an electronics package. The pump functions without the use of check valves.

Abstract: Apparatus is provided for cooling a closely grouped plurality of integrated circuit chips by forced air convection. A heat sink, having a plurality of fins and a narrow channel between each fin, is connected to a first side of a substrate and has one end protruding into an aperture in the substrate. A chip is connected directly to the one end of the sink and is electrically connected to a second side of the substrate.

Abstract: During the manufacture of Josephson junction devices, it is necessary to provide superconducting layers for electrodes. During the manufacture of semiconductors, it is necessary to provide conductive paths and leads. A layer of conducting metal or superconducting metal may be vacuum deposited in such a manner that any predetermined pattern or shape of normally conducting metal is made transversely non-conducting. The layer metal which is transversely non-conductive is vacuum deposited in the presence of an inert gas at a pressure which is high enough to cause the evaporated and deposited metal to form islands of conductive metal separated by insulating voids to provide gross electrical anisotropy.

Abstract: A data word of less than or equal to 2.sup.N bits is counted for the number of binary "1's" contained therein in log.sub.2 2.sup.N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data.

Abstract: A multichip thermal conduction module has improved cooling in a housing having a board including chips mounted on the board. The housing is divided so as to form first and second cooling portions. The chips are in the first cooling portion. Several bunches of heat conducting strands extend into the first cooling portion so that each bunch is urged into deflecting contact with a respective chip. A fluid inlet and outlet are provided in the second cooling portion.

Abstract: A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate array assembly generally multiplying successive eight bit bytes of the multiplier two bits at a time in each of four ranks to the full width multiplicand and producing a partial sum and carry at the end of each cycle. Each partial sum and carry then being fedback, aligned and added into the partial sum and carry produced during the multiplication of the next successive multiplier byte, until the multiplication is complete and at which time the final partial carry is converted and added to the final partial product to produce the final product.

Abstract: A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control one or more system's accessibility to peripheral subsystem's from a central location. It is able to provide this control with the capability of either allowing a peripheral subsystem to be concurrently accessed by more than one system or forcibly ensuring that the peripheral subsystem is exclusively accessible by only a single system.

Abstract: A computer digital logic circuit utilizing an encoded Read Only Memory (ROM) and multiplexor elements is used to translate top-level shift control signals, such as arise from instruction translation, into the low-level control of selecting data input to, and controlling the shift count in, a shif matrix during a generalized computer shift operation. ROM size is held to only 64 addresses.times.16 bits per addressed cell in controlling selectable circular, selectable sign fill, single precision or double precision (dual pass) shifting in a sixteen bit shift matrix because the ROM is addressed with only part of the top-level shift control signals. Remaining top-level signals select among encoded outputs of the ROM in four multiplexor circuit elements to produce low-level gating control signals, called preselector control, which ultimately enable selection among two registers' data and sign fill data inputs to the shift matrix. The ROM directly produces the shift count control of the shift matrix.