Abstract: The invention concerns a method for repairing transmission masks. After the mask has been inspected and the position coordinates of the mask openings have been stored, these position coordinates are compared with the position coordinates of the desired mask pattern to determine the location of defects. The mask to be repaired is then blanket coated on its front side with a photoresist. Particular photoresist regions overlying the mask defects to be repaired are exposed by non-optical or optical radiation for cross-linking the photoresist, the dose required for cross-linking depending upon the respective resist employed. The non-crosslinked portions of the photoresist are subsequently removed. Gold is then applied to the rear of the mask, with the cross-linked photoresist regions acting as a substrate. After the gold has been applied, the cross-linked photoresist regions are removed, typically by plasma etching.

Abstract: A composition and method for anistropically etching polysilicon or silicides with excellent selectivity to an underlying layer of an oxide or nitride of silicon is disclosed. A mixture of CClF.sub.3 or CCl.sub.2 F.sub.2 and ammonia is employed at moderate pressures in a reactive ion etching chamber.

Abstract: A flexible disk drive head access mechanism optimized for automated manufacture is disclosed. The mechanism is a complete subassembly. As such, the mechanism can be handled by a robot, as the mechanism is automatically mounted to the disk drive's main frame member. The mechanism comprises a stepping motor having a metal output pulley which is wrapped by a metal band. The middle of the band is welded to the motor's output pulley. The two free ends of the band are welded to a flexible, low-mass band tensioner. This tensioner is a thin, elongated member which includes a U-shaped portion which is operable to tension the band about the pulley. Attachment of the ends of the band to the tensioner not only tensions the band, but also operates to bend the tensioner slightly toward the pulley, thus causing the band to self-center itself in a 360.degree. wrap about the pulley. In this way, rotary to linear output from the mechanism is assured.

Abstract: A process for producing printed circuits including a dry substrate activation process and copper deposition without electroless plating is disclosed. The process requires fewer wet chemical baths, is less environmentally hazardous, and more efficient than conventional processes. Initially, sacrificial copper layers are laminated to the surface of a prepreg substrate and through holes are drilled therein. The sacrificial layer is then removed by etching and copper is sputter deposited upon the substrate surface and the walls of the through holes. Photoresist is then applied, exposed and developed to create the desired pattern of circuit lines. Next, copper is deposited in the photoresist channels and on the through hole walls by electroplating. After the photoresist is stripped, the exposed sputtered copper is removed by differential etching.

Abstract: A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer.

Abstract: The present invention provides an improved etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions. The composition of the etchant is 0.2-6 mole % hydrofluoric acid, 14-28 mole % nitric acid, and 66-86 mole % acetic acid/water. The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.

Abstract: A method for vacuum impregnation of sintered materials, preferably vacuum impregnation of sintered bearings parts, with dry lubricants is disclosed. The impregnation is performed in the following way. The cleaned parts to be impregnated are placed in a glass basin containing a mixture of, for example, molybdenum disulphide and graphite, a thermosetting resin, a solvent and a thermosetting resin extender. The glass basin is placed in a vacuum chamber and the vacuum chamber is then vacuum pumped for a sufficiently long time in order to evacuate the air from the pores of the sintered parts. After that air is again let in into the vacuum chamber until normal air pressure is reached. The sintered parts are taken out and are allowed to air dry. The coating is then cured.

Abstract: A new alloy material for use in electrical contacts is disclosed, comprising by weight______________________________________ Beryllium 1-2% Palladium 2-20%; and ______________________________________the balance of nickel.

Abstract: An improved flexible leader for use in conveying ink ribbon from a ribbon box to the print point of a printer or typewriter is disclosed. The leader is a U-shaped channel with top latches which protects the ribbon from operator contact and provides good ribbon tracking. Vertical raised ridges on the insides of the channel reduce frictional contact between the ribbon and the leader. The leader is easy to install.

Abstract: A process is disclosed for simultaneously etching holes in both the thick and thin portions of a dielectric layer on a semiconductor substrate. An anisotropic dry etchant is used to eliminate any significant lateral etching of the dielectric layer during etching. Thus, a mask-and-etch cycle may be eliminated from processing during integrated circuit manufacture, yet dimensional tolerances are maintained.

Abstract: A method making self-aligned semiconductors utilizing two resist masking steps to form a device; making one of the masks insoluable with respect to the other so that when a first part of the device is formed by a first mask, and a second part of the device is formed by the second masks, the parts are self-aligned when the first resist is dissolved.

Abstract: The process sequence is disclosed which applies a polycrystalline silicon gate material, then applies a chemical vapor deposition oxide over all surfaces, forming an effective sidewall on each of the polycrystalline silicon gate structures. An ion implantation step is then carried out to implant source and drain regions whose proximate edges are not aligned with the edges of the polycrystalline silicon gate material itself, due to the masking effect of the sidewall portion of the chemical vapor deposition oxide layer. Thereafter, the chemical vapor deposition oxide sidewall material is selectively removed for those FET device locations where an active FET device is desired to be formed in the operation of personalizing the read only storage or PLA product. Those locations are then ion implanted for source and drain extensions which are then self-aligned with the respective edges of the respective polycrystalline silicon gate electrodes.

Abstract: The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

Abstract: An FET driver circuit is disclosed which provides short circuit protection at the output node without reducing its performance. Grounded short circuit protection is achieved by sharing a load resistance at the output node in two parallel components, a low resistance active FET load and a high resistance active FET load. A delay element is inserted between the data input node and the gate for the low resistance active FET load. When the data input is low, both of the active FET load devices are off and the active logical FET device is on causing a low output value for the circuit. When the data input for the circuit goes high, the output capacitance is initially charged by the high resistance FET load device and is followed after a short delay, by charging through the low resistance FET load device. The low resistance FET load device cuts off current flow automatically after a predetermined period of time transpires.

Abstract: A fabrication process for a gallium arsenide MESFET device is disclosed. A feature of the invention is placing a gate structure on the gallium arsenide substrate. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate, forming a raised source region and a raised drain region. Gallium arsenide will not grow in a conductive state on top of a tungsten gate metal. The resulting MESFET device has a raised source and drain which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planer gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.

Abstract: A logic gate is disclosed employing enhancement mode MESFET gallium arsenide devices which do not require the tight process control necessary in the prior art because two such devices are employed in the gate circuit to mutually compensate for the effects of their equal deviation from nominal threshold voltages.

Abstract: In vacuum sputter cleaning and plating operations forming a patterned metallic layer on a silicon semiconductor chip, alignment is maintained by anticipating the difference in thermal expansion between the molybdenum mask and the silicon chip and forming the apertures in the molybdenum mask in a radially offset position with respect to the intended cleaning and deposition locations on the semiconductor chip, when the mask and the chip are at room temperature. Then, when the mask and the silicon chip are maintained in a concentric position and are raised to the cleaning and deposition temperature, the differential expansion of the molybdenum mask will bring the apertures therein into perfect alignment with the intended deposition locations on the silicon wafer.

Abstract: A randomly accessible memory display is disclosed wherein a latching memory panel can be placed in direct optical contact with the triggering electroluminescent panel having a similar matrix. Once the glowing light from the trigger panel shines on the photosensitive resistive layer providing positive feedback, the corresponding region in the latching memory panel is latched. In accordance with the invention, a technique is disclosed for electrically reading the latched state in any one cell. This is done by selectively propagating a high frequency sinusoidal interrogation signal through each of the Y axis lines connected to the cells and measuring any phase alteration in each of the X axis lines connected to the cells, for each Y axis line interrogated. Since the resistance of the photosensitive resistor for a particular latching cell is altered if that cell is emitting light, the impedance of the cell is changed, thereby introducing a phase shift to the interrogation signal.

Abstract: A MOSFET device structure is disclosed where the channel region has formed therein a buried layer of dopant of the same conductivity type as the source and drain, so that the depletion layers for the PN junctions at the upper and lower boundaries thereof intersect in the middle of the implanted region, effectively forming a buried insulator layer between the source and drain. The presence of this layer increases the distance between the mirrored electrostatic charges in the gate and in the bulk of the substrate beneath the MOSFET, thereby reducing the sensitivity of the threshold voltage of the device to variations in the source to substrate voltage.

Abstract: A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.