Abstract: A radio frequency (RF) switch (40) for use in a wireless communication system operated in a time delay division mode of operation. The switch includes a pair of PIN diodes (54 and 56) serially coupled between the transmitter and receiver paths of the communication system which share a common node (58) to which a bias voltage is provided. The bias voltage is switched between first and second voltage levels to alternately cause one and the other of the pin diodes to be forward biased while the other is reversed bias. In this manner the transmitter and receiver paths will be alternately shorted to alternating current ground while the other path is shorted to a common node to an antenna.

Abstract: In a personal area network, a method for including an appliance (121). The method includes steps of a) determining, by the personal area network (120), that the appliance (121) should be included in the personal area network (120); b) determining (253) that all individual members (121) of the personal area network (120) are in data communication with the personal area network (120); and c) when all individual members (121) of the personal area network (120) are in data communication with the personal area network (120), performing substeps of: i) selecting (259) a selected member (121) of the personal area network (120); ii) programming (261) security criteria relevant to the selected member (121) into the appliance (121); and iii) programming (263) security criteria relevant to the appliance (121) into the selected member (121).

Abstract: A method for encapsulating a surface of an integrated circuit to protect the surface. The surface has an outer peripheral area and an inner area to be encapsulated. A frame is provided for handling an integrated circuit package. A plurality of leads are coupled between the frame and the outer peripheral area. An encapsulation material is dispensed on the outer peripheral area covering and protecting a portion of the leads and integrated circuit. A planar encapsulation material is deposited for covering and protecting the inner area. The planar encapsulation material provides a planar surface.

Abstract: A lead frame package for housing an integrated circuit. A lead frame (11) having a plurality of leads (13) extending from at least three sides of the package. Lead frame (11) is formed having a first region (18), a transition region (19), and a second region (21). A distance between a heat sink (12) and the lead frame (11) may vary. The offset is chosen to compensate for a predetermined distance between the heat sink (12) and the lead frame (11) such that the lead frame (11) aligns to lead frame handling equipment. A single lead frame manufacturing setup can then be used. A slot (22) is formed in the lead frame (11) extending through the second region (21) and the transition region (19) into first area (18) providing a path for injecting an encapsulation material into a mold.

Abstract: A power efficient transistor (11) which operates in or near saturation having a base (16), a collector (17), and an emitter (18). A first transistor (12) having a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). The first transistor (12) is biased to operate in or near saturation under quiescent conditions. A plurality of transistors (13) are incrementally enabled or disabled to maintain the transistor (11) in or near saturation under all operating conditions. Each of the transistors (13) have a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). A plurality of drive transistors (14), enable or disable a corresponding one of each transistor of the transistors (13). Each drive transistor of the drive transistors (14) is enabled at a different voltage thereby incrementally enabling and disabling each transistor of transistors (13) maintaining transistor 11 in or near saturation.

Abstract: A radio frequency interference (RFI) gasket (10) to be used with a chassis (36) having slot panels for receiving electronic assembly boards therein wherein the RFI gasket comprises a metal bar (12) dimensioned to fit within slots of the the chassis and a metallic spring clip (14) that is contiguous with the metal bar and makes electrical contact therewith. The spring clip is compressed against the metal bar as electronic assembly boards are installed into the chassis to such that the RFI gasket makes electrical contact between the the chassis and the assembly board to inhibit RFI radiation.

Abstract: A speech-recognition system for recognizing isolated words includes pre-processing circuitry for performing analog-to-digital conversion and cepstral analysis, and a plurality of neural networks which compute discriminant functions based on polynomial expansions. The system may be implemented using either hardware or software or a combination thereof. The speech wave-form of a spoken word is analyzed and converted into a sequence of data frames. The sequence of frames is partitioned into data blocks, and the data blocks are then broadcast to a plurality of neural networks. Using the data blocks, the neural networks compute polynomial expansions. The output of the neural networks is used to determine the identity of the spoken word. The neural networks utilize a matrix-inversion or alternatively a least-squares estimation training algorithm which does not require repetitive training and which yields a global minimum to each given set of training examples.

Abstract: A method for predicting yields for integrated circuit designs for given specification limits and process variations with respect to transistor parametric variations is based on a stastical analysis starting with response surface modeling techniques that relate desired circuit outcomes as a function of a set of defined independent variables. The response surfaces are converted to discrete C.sub.pk surfaces for all combinations of the independent variables. The C.sub.pk surfaces are next converted to discrete percent yield surfaces for each of the circuit outcomes which then are combined to provide a composite yield surface comprising all desired parametric operating points of the outcomes that may be used to predict the circuit yield.

Abstract: A scan path debugger isolates and identifies hardware and software faults in a computer system containing scan path logic. A user can readily define what information is to be examined and in what format. The user can toggle between displaying information in data-aligned format or time-aligned format. The user may temporarily suspend control of the scan path debugger to allow the system to be controlled temporarily by a different, unrelated program. The user can check the operation of the system under different microcode files. The user can also save the complete logic state of the system under test, execute one or more scan path debugger instructions while observing the results, restore the saved state, execute the same or different instructions, and observe the results.

Abstract: A method for communicating between processes in a data processing system comprising a plurality of processor hosts each coupled to a network and a plurality of processes resident on different ones of said processor hosts, wherein messages are transmitted from one process to another in a logical ring. A message-holding queue is maintained at any host originating a message transmission, and it contains a copy of the message, an identifier of the initiating processor host, and an identifier of the target processor host. A forward notification message is returned to the originating host from a forwarding host when the forwarding host relays the message to another host, and an identical forward notification message is returned to the originating host by the target host when it receives the message.

Abstract: A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).

Abstract: A method for troubleshooting an electronic circuit board assembly which comprises a plurality of components interconnected by a plurality of nodes having electrical terminals without the need to de-solder. The method comprises measuring the resistance value for one of the plurality of nodes, and, if the measured resistance value does not match a target value, individually cooling or heating each of the components which are coupled to such node while simultaneously measuring the resistance value for the node, and identifying as faulty that component for which the measured resistance deviates most from the target value.

Abstract: A pulsed pressure sensor circuit (11) with increased sensitivity for measuring low pressures. A pulse generation circuit (12) is enabled by a microprocessor (28) to output a voltage pulse. The voltage pulse biases a pressure sensor (17) which has a port exposed to a pressure to be sensed. The pressure sensor (17) outputs a differential voltage which is proportional to the pressure at the port. The differential voltage is amplified by an amplifier (23) which has an output coupled to the microprocessor (28). A voltage divider circuit (26) is coupled to the pulse generation circuit (12) and has an output coupled to the microprocessor (28). The microprocessor (28) samples the voltages at the output of the amplifier (23) and the output of the voltage divider circuit (26). Microprocessor (28) then calculates the pressure using the sampled voltages and data stored in memory.

Abstract: A circuit for detecting a substance in motion. A light source (11) emits light which is received by a first photodetector (16) and a second photodetector (18). Each of the photodetectors (16) and (18) receives substantially equal light intensities from the light source (11). The first photodetector (16) generates a first output voltage (17) which corresponds to light intensity. The second photodetector (18) generates a second output voltage (19) which corresponds to light intensity. A differential amplifier (21) has a first input coupled to the first output voltage (17) and a second input coupled to the second output voltage (19). A moving substance (13) passing between the light source (11) and the first (16) or second (18) photodetectors generates a differential voltage which is amplified by the differential amplifier (21).

Abstract: A modular filter (11) that operates at low voltages and utilizes common mode feedback is described. The modular filter (11) receives an input differential signal and provides a filtered output differential signal. The modular filter (11) comprises a load circuit (15) , a first transconductor (18) , a second transconductor (24) , an amplifier (19), and a common mode amplifier (26). The first transconductor (18) has a transconductance gml and the second transconductor (24) has a transconductance g.sub.m2. The amplifier has a gain K. The modular filter (11) provides a transfer function of V.sub.o /V.sub.i =(g.sub.m1 /g.sub.m2)*((1+(sKC.sub.a /g.sub.m1))/(1+(s (C.sub.a +C.sub.b)/g.sub.m2)), where C.sub.a are capacitors (21 and 22) that capacitively couple outputs of the amplifier (19) to the load circuit (15) and C.sub.b are capacitors (27 and 28) that capacitively couples the output of the common mode amplifier (26) to the load circuit (15).

Abstract: An optocoupler package made up from a pre-assembled package having a leadframe, a voltage isolation barrier, and a body molded from a reflective plastic material. The voltage isolation barrier is fabricated as part of the body and positioned in such a way as to substantially increase the electrical flashover path between the optical source and the optical detector. An optical source mounted in the pre-assembled package subsequent to fabrication of the molded body. An optical detector is optically coupled to the optical source by reflection within the pre-assembled package, the optical detector being mounted in the pre-assembled package subsequent to fabrication of the molded body A reflective plastic cover is bonded to the pre-assembled package.

Abstract: A voltage controlled oscillator (VCO) (2) provides an output signal which has a 50% duty cycle and a frequency which depends on the voltage of a control signal (V) supplied thereto. The VCO (2) comprises first (C.sub.L) and second (C.sub.R) capacitors and first (3) and second (5) circuits. Each of the first and second circuits comprises a current supply arrangement (10, 12, 14, or 18, 20, 22) coupled to a respective one of the capacitors (C.sub.L or C.sub.R) and to receive the control signal (V), and a Schmitt trigger (6 or 16) coupled to the respective current supply arrangement and to the other capacitor, which is not coupled to the respective current supply arrangement. Each current supply arrangement of the first and second circuits alternately charges and discharges the respective capacitor, in dependence on the switching of the respective Schmitt trigger, so that the VCO (2) oscillates between the charging of the first and the charging of the second capacitor.

Abstract: A discriminator device for discriminating between two types of signal applied to an input port (EN), the first type being a binary logic signal having high and low values, and the second type of signal being a continuously variable signal or a floating voltage, the device including a voltage divider network (R1,R2) for coupling to the input port and a voltage supply (VCC) in order to provide a format signal, a second voltage divider network (R3,R4,R5) providing first and second voltage reference signals (VR1,VR2) having values intermediate the high and low values of the binary logic signal, comparators (34A, 34B) coupled to receive the format signal and the voltage reference signals, the outputs of the comparators being coupled to an output logic circuit (36-39) which provides a logic output signal of a value depending on the type of signal present at the input port.

Abstract: An environmental chamber for a transmission electron microscope, in which a specimen is held in position within the transmission electron microscope so an electron beam passes through the specimen to a detector. A removable sleeve surrounds the specimen holder and is sealed at both ends by a seal between the removable sleeve and the specimen holder to form a differential pressure chamber. Apertures are formed in the removable sleeve allowing the electron beam to pass through the specimen to the detector. A vacuum line allows gases to be removed from the differential chamber. A reactive inlet line extends into the differential chamber to allow a material to be introduced onto the specimen.

Abstract: A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal.