Abstract: A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased.

Abstract: A differential pair of transistors (Q2, Q3), the sources of which are connected to a current source (Q1); first and second input terminals (IN, VX) connected to the gates of the first and second transistors respectively; first and second output terminals (DN, DP) connected to the drains of the second and first transistors; third and fourth transistors (Q6, Q7), the sources of which are connected to a voltage supply (UDD), the drain of the third transistor being connected to the drain of the first transistor, and the drain of the fourth transistor being connected to the drain of the second transistor; the gate of the third transistor being connected to the drain of the first transistor via first switch (Q104) and connected to the drain of the second transistor via a first capacitor (C1); and the gate of the fourth transistor being connected to the drain of the second transistor via second switch (Q5) and connected to the drain of the first transistor via a second capacitor (C2).

Abstract: A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit is coupled across a first capacitor for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit is coupled across a second capacitor for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state.

Abstract: A CMOS multiplexing circuit is provided for selecting one of a plurality of input signals under control of a digital select signal for providing an output signal inverted with respect to the selected input signal. A plurality of processing channels one for each input signal and each having exactly first, second, third and fourth transistors serially connected between first and second sources of operating potential are repsonsive to the digital select signal whereby only the second and third transistors in the selected processing channels are enabled. The other processing channels supporting the remaining input signals are disabled. The first and fourth transistors of the selected processing channel are alternately enabled by one of the plurality of input signals for providing the inverse state thereof at the output formed at the interconnection of the second and third transistors.

Abstract: A high speed voltage translator provides a CMOS output signal in response to an ECL input signal which is applied to an input stage coupled between first and second power supply conductors wherein the potential developed at the output of the input stage is independent of variations in the power supply voltage. The translating stage is coupled between said first and second power supply conductors and is responsive to the potential developed at the output of the input stage for conducting a predetermined current therethrough. A feedback signal proportional to the magnitude of the predetermined current flowing through the translating stage is generated to control the potential developed at the output of the input stage so as to maintain the predetermined current at a low value to reduce the power consumption of the voltage translator.

Abstract: A balanced oscillator circuit having first and second outputs includes a transistor circuit, having internal parasitic capacitors, for providing first and second output signals at the first and second outputs of the balanced oscillator circuit. An inductor circuit is coupled between the first and second outputs such that the inductor circuit and the internal parasitic capacitors determine the frequency of oscillation of the first and second output signals. The capacitance of the internal parasitic capacitors can be varied by an external voltage applied to the transistor circuit.

Abstract: A full wave rectifier/averaging circuit for processing an input signal having a large dynamic range. A rectification circuit is responsive to the input signal for providing a first signal to a current mirror whereby the current mirror provides a second signal in response to the first signal. An averaging circuit is coupled to the current mirror to perform averaging of the second signal. An output circuit is coupled to the averaging circuit to provide an output signal at an output terminal.

Abstract: A sensor arrangement, particularly suitable for pressure sensors is disclosed, in which differential output signals from a pressure sensor are switched between two amplifiers and fed to a microcomputer where they are stored as two pairs of signals in digital form. The two pairs of signals are combined to cancel amplifier offset voltages.

Abstract: A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

Abstract: A single 3-terminal integrated circuit for controlling a switching device provides both control terminal voltage limitation and rapid turn off time. In an alternative embodiment the control circuit is contained in the same package which houses the controlled switching device.

Abstract: A flipflop circuit is responsive to a clock signal for latching the terminal logic state of the input signal at an output irrespective of the relative transistions of the input data signal and the clock signal thereby providing immunity from the meta-stable condition. The input data signal is propagated from the input through a first stage to an intermediate node during a first clock cycle. A boost signal is applied at the intermediate node via first or second transistors for driving the potential developed thereat toward the terminal logic state of the input data signal. The logic state stored at the intermediate node may be used as the output signal or passed through additional buffer stages to an output during subsequent cycles of the clock signal.

Abstract: A lamp intensity control system combines the functions of the tail light, the brake light, and the turn indicator light signals into one signal for controlling a plurality of lamps in an automobile. The tail light, brake light and turn indicator light signals are combined into one signal and modulated wherein the percent of modulation determines the intensity of the brightness of the plurality of lamps. Temperature protection is provided wherein a temperature limit circuit monitors the temperature of a SENSFET and disables the SENSFET if its temperature exceeds a predetermined magnitude. Over-current and open lamp conditions are monitored by comparator circuits. An over-current condition causes the SENSFET to be disabled. An over-temperature, over-current or open-lamp condition is signaled by a fault output signal.

Abstract: A CMOS analog multiplying circuit comprising a first transistor (1) having its current electrodes coupled between a first reference voltage line and a first node and its gate electrode coupled to a first input node having, in use, an input voltage such that said first transistor operates in its triode region, a second transistor (2) having its current electrodes coupled between said first node and an output node, said output node being coupled to a second reference voltage line, and a comparator (3) for comparing a first voltage at said first node with a second voltage at a second input node and for controlling the gate electrode of said second transistor to keep said first and second voltages substantially equal, whereby the current through said second transistor is proportional to the product of the voltages at said first and second input nodes.

Abstract: A peak detector circuit that provides a signal at an output terminal which represents the most positive peak voltage level applied at an input terminal. Comparator circuit is coupled to the input terminal and to the output terminal to determine which voltage signal thereof is more positive to provide an output current whenever the supplied input voltage exceeds the voltage at the output terminal. The output current is then amplified for providing a current to a capacitor circuit for developing a voltage across the capacitor equal to the positive peak voltage level applied at the input terminal. A buffer circuit coupled to the capacitor circuit transforms the voltage across capacitor circuit to the output terminal and includes a clamping circuit for clamping coupled between the output terminal and the comparator circuit to prevent the comparator circuit output from saturating whenever the voltage applied at the input terminal is less than that appearing at the output terminal.

Abstract: A filter cell having common mode compensation for use in a differential integrating filter includes a transconductance amplifier that comprises a pair of differentially connected transistors the bases of which are coupled to respective inputs of the filter cell and whose emitters are interconnected to a current sinking transistor while the collectors are coupled via respective output circuitry to first and second outputs of the filter cell. Circuitry is provided to set the common voltage levels at the first and second outputs of the comprising a pair of resistors commonly connected at a circuit node that is a virtual ground for differential signals and the first and second filter cell outputs respectively. The circuit node is also coupled to the base of the current sinking transistor to thereby for a common mode closed loop in conjunction with a current supply that is also coupled to the circuit node.

Abstract: A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

Abstract: A circuit for enhancing the alpha of a transistor. A current supplying circuit passes the base current of the transistor through a first and second current mirror for providing current at the emitter of the transistor such that the apparent emitter current of the transistor is made substantially equal to the collector current of the transistor.

Abstract: A method to extract at wafer probe the variation of lateral PNP basewidth of transistors formed in an integrated circuit which uses two lateral PNP devices having different and known basewidths before fabrication of the devices in the integrated circuit and then measuring the ratio of the saturation currents at wafer probe. The actual basewidth of the lateral PNP transistor is then related to the difference of the known basewidths of the two lateral PNP transistors and the ratio of the saturation measured currents thereof.

Abstract: An amplifier output stage with minimum circuitry and optimum performance for providing a SAT-to-SAT output voltage signal at an output terminal. The amplifier output stage includes a first transistor having a collector coupled to the output terminal for sourcing current thereto, a base coupled to a first supply voltage terminal, and an emitter coupled to the first supply voltage terminal. A second transistor having a collector coupled to the output terminal for sinking current thereat, a base, and an emitter coupled to a second supply voltage terminal. A third transistor having a collector, a base coupled to the base of the second transistor, and an emitter coupled to the second supply voltage terminal by a first resistor. A fourth transistor having a collector coupled to the first supply voltage terminal, a base coupled to an input terminal, and an emitter coupled to the base of the third transistor.

Abstract: A tuning circuit is provided for increasing the power transfer between first and second electrically coupled utilization circuits while controlling the effective source reflection coefficient thereby increasing the power available to the latter wherein the input signal provided at the output of the first utilization circuit is reflected back reducing the power available at the input of the second utilization circuit. The input signal is applied to the first input of the power combiner while a feedback signal proportional to the power loss between the first and second utilization circuits is applied to the second input of the power combiner. The output of the power combiner is increased by the feedback signal for compensating the power loss of the input signal such that the power available to the second utilization circuit is increased.