Abstract: In a method and apparatus for processing an image signal, luminance signals are generated for an object pixel and local pixels. A luminance dispersion value is then generated for the object pixel from the luminance signals of the object and local pixels. A control factor is determined from the luminance dispersion value, and at least one image signal of the object pixel is low-pass filtered according to the control factor.
Abstract: For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior gain value, and a prior timing signal estimation value. A timing error estimator generates a current timing error estimation value from a timing error accumulation value and the current timing signal estimation value. A current gain value of the loop filter is determined from the current timing error estimation value.
Abstract: For processing image data generated for a color filter array, classifiers are generated from the image data. A predetermined color component is determined by directional-interpolating the image data depending on the classifiers. Chrominance components are generated from linear-interpolated image data and the directional-interpolated predetermined color component. The chrominance components are directional-interpolated, and color components are extracted from the directional-interpolated chrominance components.
Abstract: A reset signal generator includes an output unit, a trip signal generator, an inverter unit, and a variation reducing unit. The output unit generates a reset signal from a pre-reset signal, and the reset signal follows a supply voltage signal before transitioning to a ground level when the supply voltage signal reaches a tripping voltage. The variation reducing unit is coupled to the inverter unit for reducing a range of the tripping voltage with temperature variations.
Abstract: For communicating data frames, a respective data frame is transmitted from each of a plurality of transmitter antennas of a transmitter. In addition, a power of any data field that is of a predetermined data type within the respective data frames is boosted to a maximum available power of the transmitter. Thus, total available power of a transmitter is efficiently used for transmitting data fields of the predetermined data type such as channel estimation preambles transmitted with time orthogonality.
Abstract: For determining FFT and GI (guard interval) modes within a receiver, a correlation signal is generated from an in-phase and quadrature (I/Q) stream. An plurality of GI mode division signals are generated by processing the correlation signal delayed by different delays. For each of the GI mode division signals, a respective peak-value position and a respective peak-value is determined to be used for determining the GI and FFT modes of the I/Q stream. The correlation calculator generates the correlation signal dependent on the FFT mode to minimize memory capacity and cost of the receiver.
Abstract: A quadrature voltage controlled oscillator includes oscillation circuits for generating in-phase and quadrature-phase oscillation signals that are used to generate in-phase and quadrature-phase output signals. A compensation circuit adjusts biasing in the oscillation circuits depending on a phase relationship between the in-phase and quadrature-phase output signals to automatically control the phase relationship between the oscillation signals.
Abstract: Contacts and/or a transistor are shared by neighboring pixel circuits in an image sensor. In addition, a common interconnect line provides common control signals for minimizing metal wiring. Such minimization of space for the shared contacts, transistor, and control signals enhances the fill factor of photodiodes in the image sensor.
Type:
Grant
Filed:
May 17, 2006
Date of Patent:
August 11, 2009
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Sung-Ho Choi, Yi-Tae Kim, Young-Chan Kim, Hae-Kyung Kong
Abstract: A charging controller includes a control node having a control voltage generated thereon for controlling a first current to a charged device and a second current to a reference device. Feedback loops are formed with amplifiers and a pull-up current source and control transistors, or with amplifiers and transfer transistors, for maintaining the second current at a constant current level during a constant current mode and for maintaining a voltage of the charged device at a constant voltage level during a constant voltage mode. Use of a pull-down current source at the control node is avoided for preventing damage to the charged device.
Abstract: A level detector within a back-bias voltage generator includes a toggling unit and a temperature detector. The toggling unit causes an enable signal to be activated when an absolute value of a back-bias voltage is less than an absolute value of a monitoring level. The temperature detector controls the toggling unit for increasing the absolute value of the monitoring level with an increase in temperature with high temperature sensitivity.
Abstract: A signal generator generates a track traversing signal, and a driver causes a pick-up to traverse across tracks of a disc in accordance with the track traversing signal. An error signal generator generates a tracking error signal from the pick-up traversing across the tracks of the disc in accordance with the track traversing signal. A parameter calculator determines a value of a calibration parameter from the tracking error signal that is generated without delay and without signal distortion from low frequency components.
Abstract: An adaptive biasing input stage includes pairs of differentially coupled amplifying and sensing field effect transistors having gates with differential inputs applied thereon. In addition, a static current source is coupled to sources of the amplifying and sensing field effect transistors at a predetermined node. Also, current mirrors are coupled to the sensing field effect transistors for forming loop mechanisms for increasing the current through the predetermined node when the differential inputs have a non-zero difference.
Abstract: A voltage-controlled oscillator (VCO) according to an aspect of the present invention includes an oscillation unit and a delay time control unit. The oscillation unit generates an oscillation signal with a frequency determined by a VCO control signal. The delay time control unit adjusts a delay of the oscillation signal in response to a change of a power supply voltage. Such a VCO is advantageously used for minimizing signal skew in a phase-locked loop (PLL).
Abstract: A solid-state imaging device includes a light sensor formed in a semiconductor substrate. In addition, the solid-state imaging device includes a light block layer with an opening formed through the light block layer over at least a portion of the light sensor. Furthermore, at least one sidewall of the light block layer facing the opening is concave shaped for reducing smear phenomenon.
Abstract: In a method and system for luminance noise filtering, a region of pixel data directly from the image sensor is used for determining a virtually filtered luminance for a pixel location within the region. Luminance noise reduction is performed using the region of pixel data directly from the image sensor such that frame memory is eliminated. In addition, the present invention provides adaptive noise filtering by selecting the virtually filtered luminance as a final luminance for a darker image and by selecting a reference luminance without virtual noise filtering for a brighter image.
Abstract: A sigma-delta modulator (SDM) includes a delay circuit and an operation circuit. The delay circuit generates multiple clock signals with different delays. The operation circuit includes a plurality of operation stages that operate with timing according to all of the clock signals for high-order sigma-delta modulation. Thus, noise may be dispersed for minimizing noise coupling. The SDM is used to particular advantage within a fractional-N phase-locked loop.
Abstract: For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.
Type:
Grant
Filed:
June 14, 2006
Date of Patent:
May 19, 2009
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Dong-Hyun Kim, Du-Heon Song, Sang-Hyun Lee, Hyeoung-Won Seo, Dae-Joong Won
Abstract: A first voltage generator generates an active power voltage at a first power line having a decoupling capacitor coupled thereto. A second voltage generator generates a standby power voltage at a second power line. A switch is coupled between the first and second power lines. The switch is closed and the second voltage generator is disabled for an active mode of operation. The decoupling capacitor speeds up charging of the second power line to the active power voltage.
Abstract: A chip card receives and processes what-ever combination of contact data and contact-less data is available to allow multiple functionalities for the chip card. A micro-computer of the chip card is adapted to simultaneously receive and process contact data from a contact interface and contact-less data from a contact-less interface. In addition, the chip card includes a power voltage selector for selecting a contact bias to supply power to the micro-computer when-ever the contact bias voltage is available since the contact bias voltage is more stable than a contact-less bias voltage.
Abstract: An impedance controller includes multiple determination units for determining which of multiple candidate codes results in a best impedance match for an I/O pad of a semiconductor device. In addition, an error prevention unit of the impedance controller prevents any undesired bit pattern from causing improper operation of the impedance controller. Furthermore, the impedance controller includes a dummy transistor array for improved linearity of impedance variation.