Abstract: A method and apparatus for scannable zero-catcher and one-catcher circuits. The catcher circuit of the present invention comprises an input stage. A feedback stage is coupled to the input stage. Scanning logic is coupled to the feedback stage. An output stage is coupled to the feedback stage.

Abstract: A gate enhanced tri-channel positive charge pump. The positive charge pump of one embodiment comprises a switching device to transfer charge from its input terminal to its output terminal, the switching terminal further comprising a substrate terminal coupled to the input terminal. A pull-up device is coupled to the switching device, the pull-up device to precharge a boot node, the pull-up device further comprising a substrate terminal couple to the input terminal of the switching device. A pull-down device is coupled to the switching device, the pull-down device to discharge the boot node, the pull-down device further comprising a substrate terminal coupled to the input terminal of the switching device. The pump also comprises a control device coupled to the pull-down device, the control device to enable and disable the pull-down device, the control device further comprising a substrate terminal coupled to a drain terminal of the control device.

Abstract: A method for practical concurrent copying garbage collection offering minimal thread blocking times. The method comprises achieving dynamic consistency between objects in an old memory space and objects in a new memory space. Threads are allowed to progress during garbage collection and threads are flipped one at a time. No read barrier is required.

Abstract: A method of implementing a micro BGA is introduced. More specifically, the method discloses packaging an integrated circuit into an integrated circuit assembly. The method first mounts polyimide tape to a lead frame. The polyimide tape serves as a substrate for the integrated circuit package. Next, a piece of elastomer is coupled to said polyimide tape. Then an integrated circuit die is attached to said elastomer. Lead beams are then bonded from bond pads on said die to said lead frame. Solder balls are attached to said lead frame. The attached solder balls may be located beyond the area of said die.

Abstract: A method for high precision charge pump regulation. The method of one embodiment comprises comparing an output feedback voltage with a reference voltage to determine whether the output feedback voltage is greater than or less than the reference voltage. In response to the comparison, either increasing a frequency for a clock signal if the output feedback voltage is less than the reference voltage, decreasing the frequency for the clock signal if the output feedback voltage is greater than the reference voltage; or disabling the clock signal if the output feedback voltage is much greater than the reference voltage. A pumped voltage is generated in response to changes to the clock signal.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A method and apparatus to provide a low voltage reference generation. The apparatus includes a reference voltage generator to receive a first input voltage signal and output a reference voltage signal. A voltage level detector electrically coupled to the reference voltage generator to receive the reference voltage signal and also receive a second input voltage signal. The voltage level detector compares the second input voltage signal to the reference voltage signal for generating an output based on the compared signals.

Abstract: A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set ‘n’ can match the address. The address is masked to determine if a thrash condition exists. Allocation to set ‘n’ is discouraged if a thrash condition is present.

Abstract: A method and apparatus for a strobe glitch protection mechanism for a source synchronous I/O link. One method of the present invention comprises separating a transfer clock having a plurality of transfer clock edges into a pointer path and a timing path. Glitches are filtered from signals on said pointer path. The pointer path and the timing path are coupled to generate latch enable signals to latch data bits.

Abstract: An apparatus for a differential amplifier with dynamic cascodes. The apparatus of one embodiment comprises a dynamic cascode bias generator. A first and second cascode transistors are coupled to the generator. A differential pair is coupled to the cascode transistors. The differential pair comprises of a first input transistor to receive an inverting input and a second input transistor to receive a non-inverting input.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: A method for automatically detecting signal levels for buffer configuration. The method of one embodiment first samples a first signal. The first signal is compared with a second signal to determine whether the first signal has a higher voltage potential than the second signal. The result of the comparison is latched. The result of the comparison is used to program buffer characteristics.

Abstract: A method and apparatus for reducing snoop stall on an external bus. One method of the present invention comprises retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of the bus transaction. Then it is determined whether the bus transaction is a snoopable memory transaction or not. If the bus transaction is a snoopable memory transaction, a snoop probe is dispatched during the first request phase packet of the transaction. Snooping devices are allowed additional bus clocks to respond to the snoop probe, thereby reducing the number of snoop stalls required to be inserted during the bus transaction.

Abstract: A method of accessing memory. The method of one embodiment first receives a first address. The first address is then decoded. A determination is made as to whether the first address indicates a top boot address.

Abstract: An apparatus for a differential redundancy multiplexor for flash memory devices. One embodiment comprises a memory array comprising a main memory element and a redundant element. A sense amp is coupled to the memory array to evaluate the main memory element and to generate a first pair of differential output signals. A redundant sense amp is coupled to the memory array. The redundant sense amp is to evaluate the redundant memory element and to generate a second pair of differential output signals. A multiplexor is coupled to the sense amp and the redundant sense amp. The multiplexor is to receive the first pair and the second pair. The multiplexor is to generate a single ended output from evaluating a single pair of differential output signals. Control logic coupled to the multiplexor to control whether the first pair or the second pair is the single pair of differential output signals evaluated.

Abstract: A method for the detection of the end-of-life for a rechargeable battery. The method of one embodiment comprises identifying a rechargeable battery. A designed capacity of the rechargeable batterty is determined. A present full charge capacity of the rechargeable battery is determined. A status of the rechargeable battery is evaluated. An end-of-life warning for the battery is issued if an end-of-life status is detected.

Abstract: A method of constructing and unrolling speculatively counted loops. The method of the present invention first locates a memory load instruction within the loop body of a loop. An advance load instruction is inserted into the preheader of the loop. The memory load instruction is replaced with a check instruction. The loop body is unrolled. A cleanup block is generated for said loop.

Abstract: A method and apparatus for configuring memory devices. A disclosed bus controller includes a storage location and a control circuit. The control circuit is coupled to perform an initialization operation when a value indicating that initialization operation is stored in the storage location. The initialization operation is selected from one of a set of initialization operations that the control circuit is capable of performing.

Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.

Abstract: An n-well resistor device and its method of fabrication. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.