Abstract: An apparatus to provide a novel bi-voltage level switching. The apparatus includes a first level shifting buffer coupled to a voltage supply, an input, and a first transistor. The first transistor coupled to the voltage supply and an output. A second level shifting buffer coupled to the voltage supply, the input and second transistor. The second transistor coupled to the output and a voltage source.

Abstract: A gate enhanced tri-channel positive charge pump. The positive charge pump of one embodiment comprises a switching device to transfer charge from its input terminal to its output terminal, the switching terminal further comprising a substrate terminal coupled to the input terminal. A pull-up device is coupled to the switching device, the pull-up device to precharge a boot node, the pull-up device further comprising a substrate terminal couple to the input terminal of the switching device. A pull-down device is coupled to the switching device, the pull-down device to discharge the boot-node, the pull-down device further comprising a substrate terminal coupled to the input terminal of the switching device. The pump also comprises a control device coupled to the pull-down device, the control device to enable and disable the pull-down device, the control device further comprising a substrate terminal coupled to a drain terminal of the control device.

Abstract: A method for incorporating bus ratio strap options in chipset logic. The method of one embodiment first fabricates a register and multiplexer in chipset logic. The register is programmed with a bus ratio setting. A bus ratio setting is selected to be the output from the multiplexer. The selected bus ratio setting is driven out from the multiplexer to output pins.

Abstract: The present invention introduces a method of implementing micro BGA. More specifically, the present invention discloses a method of packaging an integrated circuit into an integrated circuit assembly. The method of the present invention first mounts polyimide tape to a lead frame. The polyimide tape serves as a substrate for the integrated circuit package. Next, a piece of elastomer is coupled to said polyimide tape. Then an integrated circuit die is attached to said elastomer. Lead beams are then bonded from bond pads on said die to said lead frame. Solder balls are attached to said lead frame. The attached solder balls may be located beyond the area of said die.

Abstract: An apparatus is provided for mounting a Very Large Scale Integration (VLSI) chip such as a microprocessor on the back plane of a computer chassis. In one embodiment, the mounting on the computer chassis is configured to provide a current supply connection for delivering a high level of current to the microprocessor from a current source through the computer chassis. Also provided is an apparatus for mounting a VLSI chip such as a microprocessor on the chassis of a computer system in order to dissipate heat from the VLSI chip to the ambient outside the computer system through the computer chassis. Also provided is an apparatus for signal interconnections among one or several VLSI chips such as microprocessors mounted on the chassis of a computer to provide signal capacity with strong integrity. Also provided is an apparatus for mounting a power supply for a VLSI chip package on the back chassis of a computer.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.

Abstract: A method for displaying graphics in a computer system. In one embodiment, the method includes a step of receiving a stream of data into the main memory of the computer system. This stream of data comprises a series of descriptions of digital video frames and a series of indicators, each of which corresponds to a set, or a group of one or more, of the video frame descriptions. Each indicator indicates a basis for selecting a subset of the set of video frame descriptions. For example, in one embodiment thirty video frame descriptions are in each set, and a given indicator indicates that half of those thirty descriptions should be included in the corresponding subset. Then, only the fifteen video frame descriptions selected for inclusion in the subset are decompressed, and only the fifteen resulting video frames are displayed, while the other fifteen frames are dropped.

Abstract: A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.

Abstract: A method and apparatus for self initialization for charge pumps. The method of one embodiment comprises generating a pumped voltage at an output of the circuit. The pumped voltage is sent to a first switch. A determination is made as to whether the circuit is in a first power state. The first switch is activated to couple the pumped voltage to an initialization mechanism if the circuit is in said first power state. An internal pump node in the circuit is initialized to a first voltage potential. The first switch is deactivated to decouple the pumped voltage from the initialization mechanism after the internal pump node is charged to desired level.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. In one embodiment, a method of reliably re-allocating a first object stored within a block erasable nonvolatile memory includes the step of allocating space for a second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of re-allocating a first object stored within a block erasable nonvolatile memory includes the step of invalidating the first object, if the first object has an unreliable type of recovery level. Space is allocated for the second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of reliably re-allocating a first object stored within the block erasable nonvolatile memory includes the step of allocating space for the second object.

Abstract: An apparatus for a differential amplifier with dynamic cascodes. The apparatus of one embodiment comprises a dynamic cascode bias generator. A first and second cascode transistors are coupled to the generator. A differential pair is coupled to the cascode transistors. The differential pair comprises of a first input transistor to receive an inverting input and a second input transistor to receive a non-inverting input.

Abstract: A method and apparatus for configuring memory devices. A disclosed bus controller includes a storage location and a control circuit. The control circuit is coupled to perform an initialization operation when a value indicating that initialization operation is stored in the storage location. The initialization operation is selected from one of a set of initialization operations that the control circuit is capable of performing.

Abstract: A method and apparatus for self initialization for charge pumps. The method of one embodiment comprises generating a pumped voltage at an output of the circuit. The pumped voltage is sent to a first switch. A determination is made as to whether the circuit is in a first power state. The first switch is activated to couple the pumped voltage to an initialization mechanism if the circuit is in said first power state. An internal pump node in the circuit is initialized to a first voltage potential. The first switch is deactivated to decouple the pumped voltage from the initialization mechanism after the internal pump node is charged to desired level.

Abstract: A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

Abstract: A client/server system is disclosed, which includes a requester computer system coupled to a distributed network and having stored thereon demographic information associated with the requester, the demographic information available unencrypted such that the demographic information is accessible by any server within the distributed network, the demographic information being retrievable from a lookup table based upon an IP address provided by the requester to the server; and a server computer system coupled to the distributed network and customizing a block of content description language based upon the demographic information and providing the customized block of content description language to the requester.

Abstract: Many programming languages utilize reference pointers in computer code. Furthermore, some of these programming languages perform memory management in the form of garbage collection. Once such language is Java. During the execution of a garbage collection routine, the computer may need to locate all the variables containing reference values. The present invention introduces a method for run-time tracking of object references in computer code and determining which variables contain references to objects at garbage collection sites. The method of the present invention first creates a bit vector in memory. The bit vector is then initialized. Second, each variable declared in the computer program that may be used to store a reference value is assigned a unique bit within this bit vector. Each bit is maintained to indicate whether the variable it is assigned to is currently storing a reference value. Specifically, when a variable is assigned a reference value, the corresponding bit in the bit vector is set.

Abstract: Compilers are tools that generate efficient mappings from programs to machines A Java “Just In Time” runs as part of an application, and as such, it must be fast and efficient in its use of memory. To achieve good performance and further optimize code generation, the present invention introduces a method for optimizing Java performance using precompiled code. The method of the present invention first monitors the performance of program code during program execution. Then a list of program functions for possible native code compilation is created. The list may be created based upon static and dynamic analysis of the computer program. A plurality of program functions from said list of program functions is selected for optimization and native compilation. The selected program functions are precompiled into native program functions. The present invention also allows the precompiled native code reverted so that a user could explore the performance tuning until satisfactory.

Abstract: A driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.