Abstract: A comparator circuit suitably configured and synchronously operated to distinguish between the levels of two input signals and to provide the relative standing of the levels in binary format. In one form, a symmetrically organized circuit having the fundamental structure of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Appropriate constant current source biasing shifts the differential mode operation to optimize amplifier element gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitive elements of the circuit output stages. During the differential mode, the bistable multivibrator cross-coupling elements are disabled.

Abstract: A pair of narrow channel IGFET devices having separate insulated gate electrode structures formed over narrow channel regions of a substrate flanking a central enhancement region. Methods of forming the narrow channel regions using a single photolithography step and forming separate gate electrode structures overlying each using alternative processes, each generally involving two photolithography steps, are set forth.

Abstract: An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.

Abstract: A signal generator for producing, from a low voltage power supply, relatively large magnitude pulse signals of opposite polarity to a device input terminal having a parallel resistor-capacitor circuit connection to a reference voltage. A voltage multiplier powered by the low voltage power supply provides a multiplied voltage output which is stored on a first large capacitor. A second large capacitor has one terminal connected to the device input terminal. To produce the large, opposite polarity signals, a control circuit means operates in conjunction with the voltage multiplier and the first capacitor to produce a predetermined sequence of voltages on the second terminal of the second capacitor.

Abstract: Disclosed is a two-stage thermoelectric heat pumping apparatus for heating/cooling an I.C. chip. The first stage is a primary thermoelectric module sandwiched between a base made of a high thermal conductivity material and functioning as a heat source/sink and a heat conductive pad. The second stage is a secondary thermoelectric module sandwiched between the pad and a heat conductive block designed to receive a slotted I.C. chip socket at the top portion thereof and provided with a contact surface such that, upon insertion into the socket, the chip is in direct contact with said contact surface. By passing suitable currents through all the thermoelectric modules heat is pumped, in the heating mode, from the base (source) to the chip and, in the cooling mode, from the chip to the base (sink).

Abstract: A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET.

Abstract: Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity.The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.

Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions. In the course of coplanar processing, the gate electrodes and S/D regions are defined. Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions. Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions. The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs. In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs. Thereafter, a second, silicon nitride layer of controlled thickness is deposited.

Abstract: A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line.

Abstract: A volatile/non-volatile dynamic RAM cell and system in which the cell comprises a storage capacitor for volatilely storing binary information during normal RAM operation; an alterable-threshold storage capacitor for non-volatilely storing the information in non-volatile fashion during power off conditions; and an energy barrier between the two capacitors. Information can be restored to the volatile capacitor either by CCD charge transfer or by charge-pumped operation. The energy barrier facilitates efficient charge pumped restore of information. In one embodiment, the energy barrier is a high concentration substrate surface region having the same conductivity type as the substrate. Alternatively, the alterable-threshold non-volatile capacitor and the energy barrier are provided by a split-gate capacitor which has an alterable threshold non-volatile section (the non-volatile capacitor) and a non-alterable threshold section (the energy barrier).

Abstract: An improved process for eliminating parasitic sidewall transistor action associated with LOCOS isolation oxide structures. A combined oxide-nitride-oxide mask provides a large implant window and an underlying smaller oxidation window which is recessed about 11/2 microns relative to the implant window. Implantation, followed by oxidation provides a recessed isolation oxide and a buried inversion-suppressing impurity layer which spans the length of the oxide, including the "bird's beak" region.

Abstract: A method of forming planar silicon structures having recessed dielectric isolation oxide regions in which the bird's beak and bird's head associated with the silicon dioxide-silicon nitride dual mask are eliminated. After forming the pad oxide-nitride dual mask, photoresist is used for patterning the active device area and creating a photoresist overhang. Arsenic ions are then implanted and diffused in the isolation regions. Then, using a low (700.degree.-800.degree. C.) temperature wet oxidation, the doped silicon is fully converted to silicon dioxide forming a standard planar structure.A true coplanar structure is obtained by continuing the process by etching the grown oxide and causing the nitride mask to overhang the pad oxide. Then, arsenic ions of a lower energy than before are implanted and diffused in the field regions, which regions are subsequently oxidized at the same low temperature as before forming the final planar structure having completely inset oxide regions.

Abstract: An electronic circuit for energizing a plasma charge transfer type display system, utilizing a display panel having input driver circuits for selectively creating trapped charge in designated lines of the display panel and phase driver circuits for sequentially shifting that charge into prescribed display panel locations. A synchronized switching voltage supply provides abruptly alternating negative and positive voltage levels to the group of input driver circuits. The separate group of phase driver circuits is supplied with a fixed level of positive polarity voltage. Selective synchronization of the input and the phase driver circuit output voltages by way of the control logic creates large transitions of relative voltage between designated input and phase electrodes within the display panel. The large but transient voltage between the selected electrodes causes the gas within the associated display panel cells to ionize and form trapped charge adjacent the selected line phase electrodes.

Abstract: A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-region. The p+ region is coextensive with the thin, memory oxide structure. The binary state of the device is selected by applying a low voltage (e.g., +12v) to the gate and simultaneously applying a suitable voltage to the source and/or drain to induce avalanche breakdown in the channel, or not, to write the device to a "1" state or maintain the device in its original "0" state.

Abstract: A method for suppressing the objectionable visual flash associated with replacing patterns in a "plasma-charge-transfer" shift mechanism type AC plasma shift display panel. During the erase mode, the load mode, or both, the phase voltage repetition rate is reduced until the time average luminous flux is substantially below the level of human perception in a room ambient light background. Upon entry into the hold mode, the phase voltage repetition rate reverts to a high frequency. The rapid rate generates patterns in the display panel which have a time average luminous flux adequate for viewing in the ambient light background. The visual flash is thereby suppressed without degrading the normal display characteristics of the panel.

Abstract: Disclosed is a process for forming self-aligned all n.sup.+ -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n.sup.+ dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.

Abstract: Apparatus and methods for end point detection during the plasma etching of integrated circuit wafers. Etching is conducted in a chamber subjected to the vacuum of a pump drawing at a constant volumetric gas flow rate. The etchant gases entering the chamber are regulated by a controller responsive to a feedback loop sensing pressures within the chamber. Changes in the chamber's chemical composition, which occur in time proximity to the end point of etching, affect the pressure and are detected as variations in the gas flow rates. Empirical results confirm the distinctiveness and repeatability which characterize the flow variations at the end point of etching.

Abstract: The present invention pertains to a method and synchronizer circuit for controlling the counting operation of a timer/counter circuit to synchronize the read and update functions of this circuit. The synchronizer circuit is capable of establishing a search period prior to the occurrence of each update function. During each such search period, the synchronizer circuit searches for a read command. If a read command is not received by the synchronizer circuit within the search period preceding the occurrence of an update function, the synchronizer circuit allows the update function to occur without delay. If a read command is received by the synchronizer circuit within the search period preceding the occurrence of an update function, the synchronizer circuit delays the start of the update function until after termination of the read command that was received within the search period.

Abstract: A process for forming polysilicon-to-substrate contacts. The process permits the use of a polysilicon-to-substrate contact mask and eliminates the exposure of the substrate in the contact regions to the polysilicon etch. The polysilicon contact-forming conductors are formed from a layer of polysilicon by etching partially through the layer to leave a residual layer surrounding and defining the conductors; converting the residual polysilicon to oxide; and selectively etching the oxide. The result is a damage-free substrate contact region exhibiting reduced junction leakage current.

Abstract: A basic Schmitt trigger circuit is modified with additional circuit components for a two-input bistable circuit (latch). The latching Schmitt trigger circuit exhibits enhanced operating characteristics, such as fast and reliable switching between stable states. Also the circuit is compatible with design parameters and operating tolerances of integrated circuits. The latching Schmitt trigger circuit enables implementation of a fast reliable arbitration circuit in an integrated circuit version by minimizing the necessary time delay between the end of a resource request signal period and the start of an interrogate signal period.